DETAILED ACTION
The preliminary amendment filed 08 July 2024 is acknowledged. Applicant amended the title, submitted a substitute specification including the abstract under 37 CFR 1.125, submitted a replacement sheet for FIG. 1, canceled claims 1-6, and added claims 7-12. The replacement sheet for FIG. 1 has been entered. Claims 7-12 are pending and are examined on the merits below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . See MPEP § 2159.
Domestic Benefit / National Stage
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e), 120, 121, 365(c), or 386(c) is acknowledged. This application is a national stage entry under 35 U.S.C. 371 of International Application No. PCT/EP2022/085801, filed 14 December 2022. Acknowledgment is made of applicant’s claim for 371 status. See MPEP § 1893.
No other domestic benefit claim under 35 U.S.C. 119(e), 120, 121, or 365(c) is present in the Application Data Sheet.
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119(a)-(d) to German Application No. DE 10 2021 214 432.2, filed 15 December 2021. See MPEP § 213.
A certified copy of the foreign priority application is of record. It was received on 05 June 2024 and has been reviewed.
Acknowledgment is made of the English-language translation of German Application No. DE 10 2021 214 432.2 and the translator’s declaration of Jennifer Gibbs, dated 21 June 2024. The translation and declaration satisfy 37 CFR 1.55. See MPEP § 213.04.
The claims are accorded the foreign priority date of 15 December 2021 for prior-art purposes. References published after that date, including WO 2022/119743 A1, are not prior art under 35 U.S.C. 102(a)(1).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05 June 2024 was filed before the mailing date of the first Office action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. See MPEP § 609.
Additional documents cited by the Examiner in this action, and not listed on the IDS, are being made of record on form PTO-892.
Specification
The specification is objected to because of the following informalities. Applicant is requested to make the following corrections. See 37 CFR 1.71 and 1.72(a); MPEP §§ 606.01 and 608.01.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. See 37 CFR 1.72(a); MPEP § 606.01.
The following title is suggested: “METHOD FOR PRODUCING A VERTICAL POWER FINFET WITH TWO-PART CONTROL ELECTRODES AND IMPLANTED TRENCH SHIELDS, AND POWER FINFET”.
The substitute specification filed 08 July 2024 uses both “channel region” and “channel layer” for the same layer (205). See, for example, page 5 (“channel layer”) and page 7 (“channel region”). Applicant is requested to amend the specification so that this layer is referred to throughout by one term or the other, either “channel layer” or “channel region.”
Separately, claim 7 recites that the second connection region is arranged on the drift layer, while claim 9, FIG. 2, and page 7 of the substitute specification recite that the second connection region is arranged on the channel region. Applicant may wish to conform claim 7 to that stack in the next amendment.
Claim Interpretation
The claims are given their broadest reasonable interpretation consistent with the specification as it would be interpreted by one of ordinary skill in the art. MPEP § 2111.
The term “two-part control electrodes” is interpreted, in light of pages 6-7 of the substitute specification filed 08 July 2024, as control (gate) electrodes disposed in a trench and electrically insulated from a shielding region at the trench bottom, including but not limited to sidewall-spacer gates formed by a spacer process. The term is not limited to any particular number of lithography steps.
The recitation in claim 7 of “producing shielding regions below the trenches by an implantation process” is a process step. The same language, to the extent it appears as history of a finished device in claim 9, is product-by-process. Determination of patentability of the product is based on the product itself. MPEP § 2113.
The recitation “substantially in parallel” is interpreted as parallel within ordinary semiconductor-process variation.
Claim Rejections - 35 USC 112
112(b)
The following is a quotation of 35 U.S.C. 112(b):
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 7-12 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. MPEP § 2173. Each issue below is identified as antecedent basis, ambiguity, or unclear.
Unclear. The term “two-part control electrodes” in claims 7 and 9 is unclear. The substitute specification filed 08 July 2024 describes a spacer process on pages 6-7, but the claims do not require that process. It is unclear what structures fall inside and outside the term, for example a single wrap-around gate in a trench, a shield electrode plus a separate gate electrode, or two sidewall spacers. The claims recite the term as a genus. The specification discloses one species: sidewall-spacer control electrodes in the trench, electrically insulated from the shielding region at the trench bottom. Applicant may amend to the disclosed species or otherwise identify the metes and bounds of the genus.
Antecedent basis. Claim 9 recites “a shielding region” below each of the trenches. Claim 10 refers to “the shielding region.” It is unclear whether “the shielding region” in claim 10 is one of those regions, every region, or the set of regions under all trenches.
Claims 8 and 10-12 are indefinite at least by reason of their dependence on claim 7 or claim 9.
Claim Rejections - 35 USC 102 and 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention; or
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Prior Art Rejections Based on Primary Reference Krebs
Claim 9 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2023/0118158 A1 to Krebs et al. (“Krebs ’158”).
The 102(a)(2) reference is US 2023/0118158 A1, Application No. 17/788,653, PCT filed 15 February 2021, claiming priority to DE 10 2020 202 038 filed 18 February 2020, published 20 April 2023. Item-to-item matching below is to that PGPub. U.S. Patent No. 12,396,202 B2 is the same specification as issued and is listed on the PTO-892; it is not a separate 102 reference. Both documents are in English. No translation is used.
The named inventors of Krebs ’158 are Daniel Krebs, Joachim Rudhard, Alberto Martinez-Limia, Jens Baringhaus, and Wolfgang Feiler. The named inventors of this application are Daniel Krebs and Jens Baringhaus. The inventive entities are not the same. Krebs ’1581 names another inventor and was effectively filed before 15 December 2021. It is prior art under 35 U.S.C. 102(a)(2).
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Exemplary Figure 4C from Krebs ’158
Regarding independent claim 9, Krebs ’158 teaches a semiconductor body (FIGS. 1, 4C-4F and 5; ¶¶ [0022]-[0023]) having a first connection region (drain / drift region 10 and spreading region 12; FIGS. 1, 4A; ¶¶ [0023], [0053]), a drift layer (drift region 10 / spreading region 12; FIG. 1; ¶ [0023]), a channel region (channel in fin 14; FIGS. 1, 4D-4F; ¶ [0023]), and a second connection region (source region 30; FIG. 1; ¶ [0023]).
Krebs ’158 teaches trenches (“trenches 42”; FIGS. 4B-4C; ¶¶ [0052]-[0053]; etched as parallel openings about 800 nm wide and 1.4 µm deep from the source side into or toward spreading region 12) which extend from the second connection region into the drift layer and are arranged substantially in parallel.
Krebs ’158 teaches a shielding region (“gate shielding region 16”; FIGS. 1 and 4C; ¶¶ [0035], [0053]; self-aligned implant through open trench 42 so the shield lies under the trench) arranged below each of the trenches.
Krebs ’158 teaches a respective two-part control electrode (gate in the trench, insulated from gate shielding region 16; FIGS. 4F and 5; ¶¶ [0035], [0054]; a trench gate electrically insulated from the bottom shield meets “two-part control electrode” under the interpretation set out above) arranged within each trench and electrically insulated from the shielding region below the trench.
Krebs ’158 teaches fins (fins 14 remaining after lateral enlargement of trenches 42; FIGS. 4D-4F; ¶ [0054]. Krebs ’158 ¶ [0029] and FIG. 2B expressly describe “fins 300 nm wide, and a cell pitch of 800 nm”) arranged between the trenches, the fins having a width of less than 500 nm.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0118158 A1 to Krebs et al. in view of US 2019/0081142 A1 to Mauder et al. (“Mauder”)2, and further in view of US 2016/0260829 A1 to Aichinger et al. (“Aichinger”)3, subject to the 102(b)(2)(C) discussion above.
Regarding independent claim 7, Krebs ’158 teaches forming trenches (“trenches 42”; FIGS. 4B-4C), implanting a gate-shielding region (“gate shielding region 16”; FIG. 4C; implant through open trench 42) through those trenches so that a shield lies below each trench, and thereafter laterally enlarging the trenches (oxidation and etch; FIGS. 4D-4F) so that fins remain between the trenches (example width about 300 nm; FIGS. 4D-4F). A gate is then formed in the trench and insulated from the shield (FIGS. 4F and 5).
If Krebs ’158 does not expressly show a two-part (split-spacer) electrode, that feature is taught by Aichinger. See US 2016/0260829 A1, paragraphs [0089]-[0124] and FIGS. 6A-6N (spacer gates 155 along opposite trench sidewalls, dielectrically isolated from a buried shield). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the Krebs ’158 trench gate as the split sidewall spacers of Aichinger. This combination is based on KSR Rationale D. MPEP § 2143(I)(D). Finding 1. Krebs ’158 is a base method: form trenches, implant a shield through those trenches, widen the trenches so that fins remain, and form a gate in the trench insulated from the shield. A two-part spacer gate can be seen as an improvement on that base method. Finding 2. Aichinger contains a known technique applicable to that base method: spacer gates along opposite trench sidewalls, dielectrically isolated from a buried shield. Finding 3. One of ordinary skill in the art would have recognized that applying Aichinger’s spacer-gate technique to Krebs ’158 would isolate the implanted shield at the trench floor while retaining gate control on both fin sidewalls, and that those results would have been predictable.
Mauder supplies fin widths below 100 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to carry out the Krebs ’158 process with a fin width of less than 500 nm as taught by Mauder. This combination is based on KSR Rationale D. MPEP § 2143(I)(D). Finding 1. Krebs ’158 is a base method that already forms fins of about 300 nm by trench widening after the shield implant (¶ [0029]; FIGS. 4D-4F). The claimed sub-500 nm fin is an improvement already within that base method; Mauder is cited to the extent a still-narrower mesa is argued. Finding 2. Mauder contains a known technique applicable to that base method: mesa / fin width below 100 nm in a vertical power FinFET. Finding 3. One of ordinary skill in the art would have recognized that applying Mauder’s mesa-width technique to the Krebs ’158 process would yield the predictable result of a still-narrower, fully depletable fin. The 102(b)(2)(C) discussion above applies to this rejection as well.
B. Prior Art Rejections Based on Primary Reference Wolfspeed
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent No. 12,176,423 B2 to Islam et al., assigned to Wolfspeed, Inc. (“Wolfspeed”), in view of US 2019/0081142 A1 to Mauder et al. (“Mauder”), and further in view of US 2016/0260829 A1 to Aichinger et al. (“Aichinger”).
Wolfspeed is a 35 U.S.C. 102(a)(2) dated reference. It is U.S. Patent No. 12,176,423 B2, Application No. 17/108,505, filed 1 December 2020, issued 24 December 2024. The named inventors are Naeem Islam, Woongsun Kim, Daniel Jenner Lichtenwalner, and Sei-Hyung Ryu. The inventive entity is different from that of the present application. The patent was effectively filed on 1 December 2020, before the 15 December 2021 effective filing date accorded the claims. It is therefore prior art under 35 U.S.C. 102(a)(2). It is applied in this section under 35 U.S.C. 103 because it does not disclose a numerical fin width of less than 500 nm. Item-to-item matching below is to U.S. Patent No. 12,176,423 B2, FIG. 3A.
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Exemplary Figure 3A from Wolfspeed
Regarding independent claim 9, Wolfspeed teaches a semiconductor body (device 300 / layer structure 306; FIG. 3A) having a first connection region (“substrate 210”; FIG. 3A), a drift layer (“drift region 220”; FIG. 3A), a channel region (channel in “fin structure 275”; FIG. 3A), and a second connection region (“source contact 290”; FIG. 3A), trenches (“gate trenches 280”; FIG. 3A), a shielding region (“shielding regions 340” under the trench floors; FIG. 3A), a respective two-part control electrode (“gate electrode 284” insulated by “gate insulating layer 282” from 340; FIG. 3A), and fins (“fin structures 275”; FIG. 3A) arranged between the trenches. Shield doping of about 1x10^17 cm^-3 or more, including values overlapping claim 10, is disclosed.
Regarding the recitation of fins having a width of less than 500 nm, Wolfspeed shows fin structures 275 between gate trenches 280 in FIG. 3A but does not state a numerical width.
Mauder teaches a power semiconductor FinFET / mesa device in which the mesa or fin width DX13 of the channel region is smaller than 100 nm, smaller than 60 nm, or smaller than 40 nm. See Mauder paragraphs [0110]-[0125] and FIGS. 3A and 5A.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the fins 275 of Wolfspeed at a width of less than 500 nm, as taught by Mauder. This combination is based on KSR Rationale D. MPEP § 2143(I)(D). Finding 1. Wolfspeed is a base device: a vertical FinFET with fins 275, gate trenches 280, and implanted shields 340, upon which the claimed fin-width limitation can be seen as an improvement. Finding 2. Mauder contains a known technique applicable to that base device: mesa / fin width DX13 below 100 nm, and thus below 500 nm, in a vertical power FinFET. See Mauder paragraphs [0110]-[0125]. Finding 3. One of ordinary skill in the art would have recognized that applying that technique to Wolfspeed’s fins 275 would yield the predictable results of a smaller pitch and a fully depletable fin, and would have resulted in an improved device.
If “two-part control electrodes” is construed to require split sidewall-spacer gates, Wolfspeed does not expressly show that split.
Aichinger teaches a trench power device in which the gate electrode is formed as two spacer structures along opposite trench sidewalls and is partitioned from a buried diode / shield region at the trench bottom by dielectric, so that the control electrode is electrically insulated from the shield. See Aichinger paragraphs [0089]-[0124] and FIGS. 6A-6N, particularly the anisotropic etch of a conformal gate-conductor layer to form spacer gates 155.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the Wolfspeed trench gate as the split sidewall spacers of Aichinger. This combination is based on KSR Rationale D. MPEP § 2143(I)(D). Finding 1. Wolfspeed is a base device: a trench FinFET with an implanted shield 340 under gate trench 280 and a gate electrode 284 in the trench, upon which a two-part spacer gate can be seen as an improvement. Finding 2. Aichinger contains a known technique applicable to that base device: forming the gate as two spacer structures along opposite trench sidewalls, partitioned from a buried shield at the trench bottom by dielectric. See Aichinger paragraphs [0089]-[0124] and FIGS. 6A-6N. Finding 3. One of ordinary skill in the art would have recognized that applying Aichinger’s spacer-gate technique to Wolfspeed would leave the trench floor available for isolating the implanted shield while retaining gate control on both fin sidewalls, and that those results would have been predictable and would have resulted in an improved device.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent No. 12,176,423 B2 to Islam et al., assigned to Wolfspeed, Inc. (“Wolfspeed”), in view of US 2016/0260829 A1 to Aichinger and further in view of US 2019/0081142 A1 to Mauder.
Wolfspeed is a 35 U.S.C. 102(a)(2) dated reference, as set forth above.
Regarding independent claim 7, Wolfspeed teaches producing trenches (“gate trenches 280”; FIG. 3A of US 12,176,423 B2; parallel openings from the source side into drift region 220) that extend into the drift layer and are arranged in parallel, and producing shielding regions (“shielding regions 340”; FIG. 3A; implanted into the bottom surfaces of already-etched trenches 280) below the trenches by an implantation process so that a shielding region is arranged below each trench.
Aichinger teaches producing two-part (spacer) control electrodes within the trenches, each insulated from the buried region below the trench. See Aichinger as cited above.
Mauder teaches fins / mesas of width less than 100 nm, and therefore less than 500 nm, between trenches of a power FinFET, in SiC or GaN. See Mauder paragraphs [0110]-[0125].
The combination of Wolfspeed, Aichinger, and Mauder differs from claim 7 in that the references do not expressly recite, after the shield implant, a widening etch of the same trenches that leaves fins of width less than 500 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to widen the implanted trenches of Wolfspeed by etching after the shield implant, to form the resulting fins at a width of less than 500 nm as taught by Mauder, and to form two-part spacer control electrodes as taught by Aichinger. This combination is based on KSR Rationale D. MPEP § 2143(I)(D). Finding 1. Wolfspeed is a base method: etch parallel trenches and implant a shield into the open trench bottoms. The claimed post-implant widen step and sub-500 nm fin width can be seen as improvements on that base method. Finding 2. The prior art contained known techniques applicable to that base method: Mauder’s mesa / fin width below 100 nm, Aichinger’s spacer-gate process, and conventional trench-widening etches (TMAH, KOH, cyclic oxidation and strip). Finding 3. One of ordinary skill in the art would have recognized that applying those techniques to Wolfspeed—widening the implanted trench to remove sidewall dose and shrink the mesa, and forming spacer gates insulated from the floor shield—would yield predictable results and an improved process. Claim 8’s implant-energy window of 30 to 2700 keV is an ordinary aluminum-in-SiC energy span for placing a shield at the trench floor and does not patentably distinguish the method.
C. Prior Art Rejections Based on Primary Reference Dongguan
Claims 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over CN 111627983 A to Dongguan (cited on the IDS) in view of US 2019/0081142 A1 to Mauder et al. (“Mauder”).
Regarding independent claim 9, Dongguan teaches a power FinFET comprising a semiconductor body (Example 1; FIG. 2; ¶¶ [0033]-[0035]) having a first terminal region (first terminal / drain; FIG. 2), a drift layer (drift layer on the first terminal; FIG. 2) on the first terminal region, a channel region (channel on the drift; FIG. 2) on the drift layer, and a second terminal region (source-side terminal; FIG. 2), trenches (trenches from the second terminal into the drift; FIG. 2; Example 3, FIGS. 4-8) extending from the second terminal region into the drift layer, a shielding zone (shielding zone below each trench; FIG. 2; ¶ [0028]) arranged below each trench, a bipartite control electrode (bipartite control electrode in each trench, insulated from the shielding zone; FIG. 2; Example 3) arranged within each trench and electrically insulated from the shielding zone below the trench, and fins (fins between the trenches; FIG. 2) arranged between the trenches. Claim 9 is a product claim and does not require the process order of claim 7.
Dongguan does not expressly recite a numerical fin width of less than 500 nm.
Mauder teaches a power semiconductor FinFET / mesa device, including embodiments in SiC and GaN, in which the mesa or fin width DX13 of the channel region is smaller than 100 nm, smaller than 60 nm, or smaller than 40 nm. See Mauder paragraphs [0110]-[0125] and FIGS. 3A and 5A.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the fins of Dongguan with a width of less than 500 nm, as taught by Mauder. This combination is based on KSR Rationale D (applying a known technique to a known device ready for improvement to yield predictable results). MPEP § 2143(I)(D). Finding 1. Dongguan is a base device: a vertical power FinFET with trenches, a shield under each trench, a control electrode in the trench, and fins between the trenches, upon which the claimed fin-width limitation can be seen as an improvement. Finding 2. Mauder contains a known technique applicable to that base device: setting mesa / fin width DX13 of the channel region below 100 nm, 60 nm, or 40 nm in a vertical power FinFET, which is less than 500 nm. See Mauder paragraphs [0110]-[0125] and FIGS. 3A and 5A. Finding 3. One of ordinary skill in the art would have recognized that applying Mauder’s mesa-width technique to the Dongguan FinFET would yield the predictable results of a smaller cell pitch and a fully depletable fin, and would have resulted in an improved device.
Regarding claim 10, Dongguan discloses a shielding-zone doping concentration of at least 1x10^18 cm^-3. See Dongguan paragraph [0016].
Regarding claim 11, Dongguan and Mauder each disclose a SiC semiconductor body.
Regarding claim 12, Mauder discloses that the semiconductor body may comprise GaN. See Mauder paragraph [0180]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute GaN for SiC in the Dongguan device, as taught by Mauder. This combination is based on KSR Rationale B (simple substitution of one known element for another to obtain predictable results). MPEP § 2143(I)(B). Finding 1. Dongguan is a SiC power FinFET that differs from claim 12 by the semiconductor-body material. Finding 2. The substituted components and their functions were known: Mauder paragraph [0180] teaches that the semiconductor body of such a device may comprise GaN, and SiC and GaN are both known wide-bandgap power-device materials that provide a high critical field. Finding 3. One of ordinary skill in the art could have substituted GaN for SiC, and the results of that substitution (high-field blocking and high mobility in a vertical FinFET) would have been predictable.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy to prevent the unjustified or improper timewise extension of the right to exclude granted by a patent and to prevent multiple patents claiming patentably indistinct variations. See MPEP § 804.
A nonstatutory double patenting rejection over U.S. Patent No. 12,396,202 B2 is reserved. That patent issued 19 August 2025 from Application No. 17/788,653 and claims a vertical FinFET with a semiconductor fin, source, drift, channel in the fin, gate, gate dielectric, and a p-doped gate shielding region below the gate connected to source. Present claims 9-12 are directed to a closely related FinFET cell. A full claim-by-claim mapping is not set out in this action. If applicant removes Krebs ’158 as prior art under 35 U.S.C. 102(b)(2)(C), a terminal disclaimer or a showing of patentable distinctness will be required. See MPEP § 804.
Conclusion
A shortened statutory period for reply is set to expire THREE (3) MONTHS from the mailing date of this communication. Extensions of time may be available under the provisions of 37 CFR 1.136(a). In no event, however, may a reply be timely filed after SIX (6) MONTHS from the mailing date of this communication.
Claims 7-12 are rejected.
The International Search Report and Written Opinion in PCT/EP2022/085801 (EPO as ISA, mailed 23 March 2023) found original method claims corresponding to present claim 7 inventive over Dongguan, Mauder, and Aichinger, and found original device claims corresponding to present claim 9 obvious over Dongguan in view of Mauder. This action follows that device-side conclusion as a 103 rejection only. No 102 is applied over Dongguan, because Dongguan does not expressly disclose a fin width of less than 500 nm. Wolfspeed (Islam et al., U.S. Patent No. 12,176,423 B2) and Krebs ’158, which were not applied by the ISA, are additionally of record. This action does not adopt the ISA conclusion that the method is free of 35 U.S.C. 103.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN P DULKA whose telephone number is (571)270-7398. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ELISEO RAMOS-FELICIANO can be reached at (571)272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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19 September 2026
/John P. Dulka/Primary Examiner, Art Unit 2817
1 The exception of 35 U.S.C. 102(b)(2)(C) is not self-executing. Common assignment on the face of the two applications does not, by itself, exclude Krebs ’158. Different inventive entity is why 35 U.S.C. 102(a)(2) applies; it is not a ground of exclusion. If applicant establishes that the subject matter disclosed and the claimed invention were owned by the same person, or subject to an obligation of assignment to the same person, not later than the effective filing date of the claimed invention, the exception may apply. See MPEP § 2154.02(c). Until that showing is made, Krebs ’158 is applied. Even if the exception is later established, U.S. Patent No. 12,396,202 B2 remains available for nonstatutory double patenting.
2 IDS provided
3 IDS provided
Prosecution Insights