Prosecution Insights
Last updated: August 30, 2026
Application No. 18/716,676

MULTI-SLOT PHYSICAL DOWNLINK CONTROL CHANNEL MONITORING

Non-Final OA §102§103
Filed
Jun 05, 2024
Priority
Jan 05, 2022 — EU PCT/EP2022/050112 +1 more
Examiner
PHUNG, LUAT
Art Unit
2468
Tech Center
2400 — Computer Networks
Assignee
Nokia Corporation
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
1y 5m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
466 granted / 610 resolved
+18.4% vs TC avg
Moderate +12% lift
Without
With
+12.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
34 currently pending
Career history
654
Total Applications
across all art units

Statute-Specific Performance

§101
4.8%
-35.2% vs TC avg
§103
57.5%
+17.5% vs TC avg
§102
22.7%
-17.3% vs TC avg
§112
8.0%
-32.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 610 resolved cases

Office Action

§102 §103
CTNF 18/716,676 CTNF 82529 DETAILED ACTION This action is in response to the application filed on 5 June 2024. Claims 30-49 are under examination. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Specification 06-31 AIA The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 30, 32, 39, 41, and 48 are rejected under 35 U.S.C. § 102( a)(1 ) as being anticipated by Lenovo et al., “PDCCH monitoring enhancements for NR from 52.6 GHz to 71GHz,” 3GPP Draft R1-2109898, Oct. 1, 2021, as recited in the IDS . Regarding claim 30, Lenovo discloses determining that a search space relates to a subcarrier spacing and to multi-slot physical downlink control channel monitoring, wherein Lenovo discloses “Proposal 1: For supporting NR between 52.6 GHz and 71 GHz with high subcarrier spacing values including 480kHz and 960kHz, support Alt 2 i.e., extension of (X, Y) PDCCH monitoring span for multi-slot PDCCH monitoring.” (Sec. 2) Lenovo further discloses receiving a search space information element that defines a bitmap that defines a number of slots with monitoring occasions, wherein Lenovo discloses “support additional slot-level bitmap for indicating PDCCH monitoring slots within the multi-slot duration.” (Sec. 2) Lenovo further discloses receiving a duration parameter that defines a length of a monitoring window, wherein Lenovo discloses enhancing search-space configuration to support PDCCH monitoring periodicity and corresponding duration for multi-slot monitoring. (Sec. 2, Proposal 2). Lenovo further discloses determining actual monitoring slots for each period of the monitoring window, wherein Lenovo discloses slot-level bitmap indication of slots where PDCCH monitoring is configured for multi-slot monitoring. (Sec. 2, Proposal 3) Lenovo further discloses monitoring a physical downlink control channel corresponding to the search space based on the defined duration parameter, wherein Lenovo discloses multi-slot PDCCH monitoring based on configured monitoring duration and bitmap-defined monitoring slots. (Figs. 2, 3) Regarding claim 32, Lenovo further discloses wherein the number of slots comprises up to eight slots, wherein Lenovo discloses “for 8 slots, the bitmap will be 14*8 bits long” for multi-slot monitoring configurations. (Sec. 2) Claim 39 recites subject matter substantially similar to that of claim 30 in apparatus form and is similarly rejected. Claim 41 recites subject matter substantially similar to that of claim 32 in apparatus form and is similarly rejected. Claim 48 recites subject matter substantially similar to that of claim 30 in computer-readable-medium form and is similarly rejected . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries set forth in Graham v. John Deere Co. , 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim s 31, 33-35, 40, 42-44, and 49 are rejected under 35 U.S.C. § 103 as being unpatentable over Lenovo et al., “PDCCH monitoring enhancements for NR from 52.6 GHz to 71GHz,” 3GPP Draft R1-2109898, Oct. 1, 2021, in view of Intel Corporation, “Discussion on PDCCH monitoring enhancements for extending NR up to 71 GHz,” 3GPP Draft R1-2111484, Nov. 6, 2021, both as recited in the IDS . Regarding claim 31, Lenovo does not specifically disclose: deriving an offset from an offset and periodicity parameter which defines a location of the monitoring window relative to a predefined reference point; and deriving a periodicity from the offset and periodicity parameter. Intel discloses “monitoringSlotPeriodicityAndOffset” parameters and duration configuration for PDCCH monitoring windows (Intel, Section 4). It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate Intel’s periodicity and offset parameter configuration into Lenovo’s multi-slot PDCCH monitoring configuration in order to flexibly configure monitoring-window timing and periodicity. Regarding claim 33, Lenovo does not specifically disclose: wherein, when the duration parameter is less than or equal to eight slots, the method further comprises determining bits up-to a number of bits of the duration parameter as valid bits in the bitmap. Intel discloses configuring monitoring durations and periodicities for PDCCH monitoring windows (Intel, Section 4). It would have been obvious to one of ordinary skill in the art at the time of the invention to limit valid bitmap bits according to the configured duration parameter as a predictable implementation technique for configuring slot monitoring within a finite monitoring duration. Regarding claim 34, Lenovo does not specifically disclose: wherein, when the duration parameter is greater than eight, the method further comprises creating a new bitmap by repeating the bitmap; and considering up-to a number of bits of the duration parameter as valid bits in the new bitmap. Intel discloses configurable monitoring periodicities and durations for monitoring windows (Intel, Section 4). It would have been obvious to one of ordinary skill in the art at the time of the invention to repeat bitmap patterns for monitoring durations exceeding the original bitmap size as a predictable implementation technique for extending slot-monitoring configurations over larger monitoring windows. Regarding claim 35, Lenovo does not specifically disclose: wherein the offset parameter aligns a starting position of the monitoring window with a starting position of a slot group X. Intel discloses adapting monitoring positions according to slot offsets in X-slot groups (Intel, Section 4). It would have been obvious to one of ordinary skill in the art at the time of the invention to align monitoring-window positions with slot-group boundaries in order to simplify monitoring-window scheduling and synchronization. Claim 40 recites subject matter substantially similar to that of claim 31 in apparatus form and is similarly rejected. Claims 42-44 recite subject matter substantially similar to that of claims 33-35, respectively, in apparatus form and are similarly rejected. Regarding claim 49, Lenovo does not specifically disclose: deriving an offset from an offset and periodicity parameter which defines a location of the monitoring window relative to a predefined reference point; deriving a periodicity from the offset and periodicity parameter; and wherein the number of slots comprises up to eight slots. Intel discloses “monitoringSlotPeriodicityAndOffset” parameters and duration configuration for PDCCH monitoring windows (Intel, Section 4). Lenovo further discloses “for 8 slots, the bitmap will be 14*8 bits long” for multi-slot monitoring configurations. It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate Intel’s periodicity and offset parameter configuration into Lenovo’s multi-slot PDCCH monitoring configuration in order to flexibly configure monitoring-window timing and periodicity while supporting up to eight-slot monitoring configurations . 07-21-aia AIA Claim s 36-38 and 45-47 are rejected under 35 U.S.C. § 103 as being unpatentable over Lenovo et al., “PDCCH monitoring enhancements for NR from 52.6 GHz to 71GHz,” 3GPP Draft R1-2109898, Oct. 1, 2021, in view of Intel Corporation, “Discussion on PDCCH monitoring enhancements for extending NR up to 71 GHz,” 3GPP Draft R1-2111484, Nov. 6, 2021, and further in view of Huawei et al., “Enhancement on PDCCH monitoring,” 3GPP Draft R1-2106443, Aug. 7, 2021, all three as recited in the IDS . Regarding claim 36, Lenovo-Intel does not specifically disclose: wherein the actual monitoring slots are dependent upon a size of a slot group X. Huawei discloses that “the unit of monitoringSlotPeriodicityAndOffset is changed to X-slots, with X=4 for 480 kHz and X=8 for 960 kHz.” It would have been obvious to one of ordinary skill in the art at the time of the invention to configure monitoring slots according to slot-group size in order to support varying subcarrier spacings and monitoring periodicities. Regarding claim 37, Lenovo-Intel does not specifically disclose: wherein, when the duration parameter is less than or equal to a duration of the slot group X, the method further comprises considering up-to a number of bits of the duration parameter as valid bits in a bitmap. Huawei discloses slot-group-based monitoring units dependent on X-slot groups, and Intel discloses configurable monitoring durations and periodicities for monitoring windows. It would have been obvious to one of ordinary skill in the art at the time of the invention to limit valid bitmap bits according to the duration parameter and slot-group duration in order to properly map monitoring occasions to configured slot-group windows. Regarding claim 38, Lenovo-Intel does not specifically disclose: wherein, when the duration parameter is greater than a duration of the slot group X, the method further comprises creating a new bitmap by repeating the bitmap; and considering up-to a number of bits of the duration parameter as valid bits in the new bitmap. Huawei discloses slot-group-based monitoring configurations using X-slot units, and Intel discloses configurable monitoring periodicities and durations for monitoring windows. It would have been obvious to one of ordinary skill in the art at the time of the invention to repeat bitmap patterns for monitoring durations exceeding a slot-group duration as a predictable implementation technique for extending monitoring configurations across larger slot-group windows. Claims 45-47 recite subject matter substantially similar to that of claims 36-38, respectively, in apparatus form and are similarly rejected . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure (see form 892) . Any inquiry concerning this communication or earlier communications from the examiner should be directed to LUAT T PHUNG whose telephone number is (571)270-3126. The examiner can normally be reached on M-F 9 AM - 6 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marcus Smith can be reached on (571) 272-3988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Luat Phung/ Primary Examiner, Art Unit 2468 Application/Control Number: 18/716,676 Page 2 Art Unit: 2468 Application/Control Number: 18/716,676 Page 3 Art Unit: 2468 Application/Control Number: 18/716,676 Page 4 Art Unit: 2468 Application/Control Number: 18/716,676 Page 5 Art Unit: 2468 Application/Control Number: 18/716,676 Page 6 Art Unit: 2468 Application/Control Number: 18/716,676 Page 7 Art Unit: 2468 Application/Control Number: 18/716,676 Page 8 Art Unit: 2468 Application/Control Number: 18/716,676 Page 9 Art Unit: 2468 Application/Control Number: 18/716,676 Page 10 Art Unit: 2468
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Prosecution Timeline

Jun 05, 2024
Application Filed
May 20, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
89%
With Interview (+12.3%)
3y 8m (~1y 5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 610 resolved cases by this examiner. Grant probability derived from career allowance rate.

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