Prosecution Insights
Last updated: August 16, 2026
Application No. 18/716,880

OPTOELECTRONIC COMPONENT, OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING A COMPONENT

Non-Final OA §102§112
Filed
Jun 05, 2024
Priority
Dec 09, 2021 — DE 10 2021 132 559.5 +1 more
Examiner
RAHMAN, MOHAMMAD A
Art Unit
Tech Center
Assignee
Ams-osram AG
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
486 granted / 559 resolved
+26.9% vs TC avg
Moderate +11% lift
Without
With
+10.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
40 currently pending
Career history
583
Total Applications
across all art units

Statute-Specific Performance

§101
2.8%
-37.2% vs TC avg
§103
46.8%
+6.8% vs TC avg
§102
30.2%
-9.8% vs TC avg
§112
18.5%
-21.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 559 resolved cases

Office Action

§102 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claims 32-60 are pending and have been examined. Priority Acknowledgment is made of applicant's claim for foreign benefit based on DE10 2021 132 559.5 filed on 12/09/2021. The instant applicant is a 371 of PCT/EP2022/085135 filed on 12/09/2022. Claim Rejections - 35 USC § 102 The following is a quotation of 35 U.S.C. 102(a)(1) that forms the basis for the rejection set forth in this Office action: (a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless— (1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention; Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document. Claims 32-35, 37-39, 41, 45, 47 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pfeuffer et al. (US 20220406757 A1 – hereinafter Pfeuffer. US 20220406757 A1 with same content of WO/2021/037568 published on 04/03/2021). Regarding Claim 32, Pfeuffer teaches an optoelectronic component with an epitaxial layer sequence (see the entire document; Figs. 27-30; specifically, ([0006] - [0170]), and as cited below), comprising: a functional inner region comprising a first electrical contact (14 – Figs. 27-30 – [0170]) and a second electrical contact (5 – also [0166]) opposite the first electrical contact (14), and semiconductor layers (3, 4 – [0162]) arranged between the first electrical contact (14) and the second electrical contact (5) being configured to generate light ([0090]), wherein the semiconductor layers comprise a base area that increases towards the second electrical contact (shown in Fig. 29); a dielectric passivation layer (21 – [0163]) on sidewalls of the semiconductor layers (3, 4) configured; and a mirror layer (34 – [0170] – 34 is a reflective layer equivalent to “mirror”) surrounding the passivation layer (21) at a distance thereby forming a gap (Cavity – [0169]- Fig. 30), wherein the second electrical contact (5) and a plane of the gap surrounding the second electrical contact form a light-emitting surface, wherein the semiconductor layers comprise a first semiconductor layer (4) having a first dopant type (n-doped – [0119]) electrically connected to the first contact (14), a second semiconductor layer (3) of a second doping type (p-doped) electrically connected to the second contact (5), and an active layer (43) arranged between the first and second semiconductor layers ([0006] – “At least one active region is arranged between the first semiconductor layer sequence and the second semiconductor layer sequence”), and wherein regions of the epitaxial layer sequence, on which the mirror layer is arranged, comprise at least one of the first semiconductor layer (4), the second semiconductor layer (3) or the active layer. Regarding Claim 33, Pfeuffer teaches the optoelectronic component according to claim 32, wherein the mirror layer (34) is electrically conductive and contacts the second electrical contact ([0165] states 34 is a contact element – therefore electrically conductive and contacts layer 5). Regarding Claim 34, Pfeuffer teaches the optoelectronic component according to claim 32, further comprising an electrically conductive transparent material (36 – [0170]) extending at least partially over the gap (Cavity) and contacting the second electrical contact (5). Regarding Claim 35, Pfeuffer teaches the optoelectronic component according to claim 34, wherein the electrically conductive transparent material comprises ITO and/or extends areal over the second electrical contact and the gap or extends as a bridge from the second electrical contact at least to the mirror layer (Fig. 30). Regarding Claim 37, Pfeuffer teaches the optoelectronic component according to claim 32, wherein the mirror layer (34) comprises at least one of the following: a metallic electrically conductive layer comprising silver, gold, platinum or another material that is highly reflective for the light generated, a sequence of layers with different refractive indices, or a DBR mirror (34 is a contact layer, as such electrically conductive – [0170]). Regarding Claim 38, Pfeuffer teaches the optoelectronic component according to claim 32, wherein the gap is, in a plan view of the light-emitting surface, circular or square or polygonal or is oriented in its shape to crystal lattice planes of the epitaxial layer sequence (the Cavity is circular in Fig. 30). Regarding Claim 39, Pfeuffer teaches the optoelectronic component according to claim 32, wherein the mirror layer (34) comprises a parabolic shape opening in a direction of the light-emitting surface (Fig. 30). Regarding Claim 41, Pfeuffer teaches the optoelectronic component according to claim 32, wherein the mirror layer opens substantially in a funnel shape in a direction of the light-emitting surface (See Fig. 30). Regarding Claim 45, Pfeuffer teaches the optoelectronic component according to claim 32, wherein the active layer comprises at least one of the following: one or more quantum well structures, a quantum well intermixing in an area of side walls, or an enlargement of a band gap in a region of the side walls ([0006]). Regarding Claim 47, Pfeuffer teaches an optoelectronic device comprising: a plurality of components according to claim 32; and at least one control layer on which the plurality of components are arranged and electrically contacted (layer 33 in Fig. 30 – [0165]). Allowable Subject Matter Claims 36, 40, 42-44, 46, 48 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is the Examiner’s Reasons for Allowance: The prior art fails to disclose and would not have rendered obvious: Regarding claim 36: The optoelectronic component according to claim 32, wherein the gap comprises at least one of the following: a transparent, non-conductive material, which at least partially fills the gap, a converter material comprising quantum dots or a polymer provided with converter particles or organic fluorescent dyes, or a gas so that the gap is at least partially free of a solid material. Regarding claim 40: The optoelectronic component according claim 32, wherein an opening angle between the mirror layer and a normal to the light-emitting surface is larger, at least in some regions, than an opening angle between the sidewalls of the semiconductor layers and the normal to the light-emitting surface, wherein an opening angle between the mirror layer and a normal to the light-emitting surface is smaller, at least in some regions, than an opening angle between side walls of the semiconductor layers and the normal to the light-emitting surface, or wherein an opening angle between the mirror layer and a normal to the light-emitting surface is, at least in some regions, substantially the same as an opening angle between the side walls of the semiconductor layers and the normal to the light-emitting surface. Regarding claim 42: The optoelectronic component according to claim 32, wherein a ratio of distances from the mirror layer to centers of the first and second contacts, respectively, is different from a ratio of distances between the sidewalls of the semiconductor layers and the centers of the first and second contacts, respectively. Regarding claim 43: The optoelectronic component according to claim 32, wherein a distance between the mirror layer and the sidewalls of the semiconductor layers in a region of the first contact depends on an angle between a normal to the light-emitting surface and the sidewalls of the semiconductor layers and a thickness of the epitaxial layer sequence. Regarding claim 44: The optoelectronic component according to claim 43, wherein the distance is given by twice an arctan of the angle between a normal to the light-emitting surface and the sidewalls of the semiconductor layers multiplied by the thickness of the epitaxial layer sequence. Regarding claim 46: The optoelectronic component according to claim 32, further comprising an insulating layer arranged on a side of the first contact and comprising at least two openings comprising an electrically conductive material, wherein the material in the first opening contacts the first contact and the material in the second opening contacts at least one of the mirror layer and a region on which the mirror layer is arranged. Regarding claim 48: The optoelectronic device according to claim 47, wherein a distance between two components corresponds to at least a distance between two opposite points of the mirror layer in a region of the light-emitting surface. REASON FOR ALLOWANCE Claims 49-60 are allowed over prior art. The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14). Regarding claim 49, the reference(s) of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge do(es) not teach or render obvious, at least to the skilled artisan, the instant invention regarding a method in their entirety (the individual limitations may be found just not in combination with proper motivation). The most relevant prior art reference(s) US 20170170360 A1 to Bour) substantially teach(es) some of limitations in claim 29 as below: providing a growth substrate (102 – 10A – [0107]); forming an areal epitaxial layer sequence with an n-doped semiconductor layer (104 – [0108]), a p- doped semiconductor layer (112 – [0112]) and an active layer (108 – [0112]) arranged in between; structuring a first surface of the epitaxial layer sequence such that, in plan view of the first surface, a surface area accessible to a first etching process encloses an inner surface (Fig. 10-B); conducting the first etching process (Fig. 10A-B – [0109]) and creating a mesa trench in the accessible surface area such that an inner region with inclined side flanks is created, wherein the mesa trench exposes at least the active layer (108) of the epitaxial layer sequence; structuring a second surface (Figs. 10B-C) of the epitaxial layer sequence opposite the first surface such that, in plan view of the second surface, areas remain accessible to a second etching process (Figs. 10B-10C), which lie at least partially above the mesa trench, but not the limitations of “conducting the second etching process such that a continuous gap is created around the inner region and the side flank of the epitaxial layer sequence opposite the inner region is at least partially inclined relative to a normal” as recited in claim 49. Therefore, the claim 49 is deemed patentable over the prior art. Regarding claims 50-60, they are allowed due to their dependencies on claim 49. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMAD A RAHMAN/ Primary Examiner, Art Unit 2898
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Prosecution Timeline

Jun 05, 2024
Application Filed
Jul 23, 2026
Non-Final Rejection mailed — §102, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
98%
With Interview (+10.9%)
2y 8m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 559 resolved cases by this examiner. Grant probability derived from career allowance rate.

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