DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pat. Pub. No. US 20210066262 A1 to Liu et al. (hereinafter “Liu”).
Regarding claim 1, Liu teaches a micro light-emitting diode, comprising:
an epitaxial layer (layers of light emitting unit 100; fig. 4) [0020] comprising a first semiconductor layer (semiconductor layer 111; fig. 4) [0021], an active layer (113; fig. 4) [0021], and a second semiconductor layer (semiconductor layer 112; fig. 4) [0021] arranged in sequence (the two semiconductor layer being disposed on both sides of the active layer), wherein the epitaxial layer (100) has a first surface (bottom surface in fig. 4) and a second surface (top surface in fig. 4) arranged opposite each other (on opposing sides), the first semiconductor layer (111) is located on a side of the epitaxial layer (100) close to the first surface (bottom), the epitaxial layer (100) is configured with a mesa (area of 111 in physical contact with electrode 121, hereinafter “mesa”), and the mesa (mesa) is exposed from the first semiconductor layer (111) and faces the second surface (top); and a dielectric layer (protective layer 500 comprising silicon, silicon oxide, silicon nitride, or epoxy; fig. 4) [0034] covering the first surface (bottom) and at least a portion of a side wall (lateral side) of the epitaxial layer (100), wherein a height H1 (distance 500 is in contact with 111) of the dielectric layer (500) on the side wall (lateral side) of the epitaxial layer (100) is less than a height of the mesa (height of 111 on the mesa side is greater than 500 on the sidewall).
Regarding claim 5, Liu teaches the micro light-emitting diode according to claim 1, wherein a material of the dielectric layer (500) comprises silicon oxide, silicon nitride, titanium oxide, aluminum oxide, or magnesium fluoride [0034].
Regarding claim 11, Liu teaches the micro light-emitting diode according to claim 1, wherein a minimum size of the micro light-emitting diode (structure 100) is 0.5 to 5 μm, 5 to 10 μm, 10 to 20 μm, 20 to 50 μm, or 50 to 100 μm [0032].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3, 4, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Liu as applied to claim 1 above, and further in view of U.S. Pat. Pub. No. US 20220173267 A1 to Teo et al. (hereinafter “Teo”).
Regarding claim 3, Liu does not teach the micro light-emitting diode according to claim 1, wherein a thickness D1 of the dielectric layer on the side wall of the epitaxial layer is greater than 0 μm and less than or equal to 2 μm.
Teo, however, teaches a micro light-emitting diode (fig. 2A) comprising semiconductor layers and an active layer (204n & p, and 206, respectively) wherein a thickness D1 of the dielectric layer (217b or 217a) [0088] on the side wall (lateral side) of the epitaxial layer (stack of layers including 204n, 206, etc.) is greater than 0 μm and less than or equal to 2 μm (1 μm) [0102].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the thickness of the dielectric layer of Liu to comprise a thickness of claim 3 to effectively insulate the active layer [0088].
Regarding claim 4, Liu does not teach the micro light-emitting diode according to claim 1, wherein a thickness D2 of the dielectric layer on the first surface is greater than or equal to 0.03 μm and less than or equal to 2 μm.
Teo, however, teaches a micro light-emitting diode (fig. 2A) comprising semiconductor layers and an active layer (204n & p, and 206, respectively) wherein a thickness D1 of the dielectric layer (217b or 217a) [0088] on the side wall (lateral side) of the epitaxial layer (stack of layers including 204n, 206, etc.) is greater than 0.03 μm and less than or equal to 2 μm (1 μm) [0102].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the thickness of the dielectric layer of Liu to comprise a thickness of claim 3 to effectively insulate the active layer as taught by Teo [0088].
Regarding claim 12, Liu does not teach the micro light-emitting diode according to claim 1, wherein a thickness of the epitaxial layer is 1 to 5 μm.
Teo, however, teaches a micro light-emitting diode (fig. 1J) wherein a thickness of the epitaxial layer (semiconductor layers 104 including an active layer; fig. 1J) [0045] is 1 to 5 μm [0046].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the diode of Liu to comprise a size according to the limitations of claim 12 to minimize the device while maximizing light-emitting area of the epitaxy as taught by Teo [0007].
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Liu as applied to claim 1 above, and further in view of U.S. Pat. Pub. No. US 20180277524 A1 to Moon et al. (hereinafter “Moon”).
Regarding claim 6, Liu does not teach the micro light-emitting diode according to claim 1, wherein at least a partial region of the first surface is configured as a rough region formed by a regular or irregular pattern, and the rough region is formed after a portion of the epitaxial layer is removed.
Moon, however, teaches a micro light-emitting diode (1050; fig. 19A) [0150] wherein at least a partial region (region of 1157; fig. 15D) [0174] of the first surface (surface of 1157) is configured as a rough region (comprising grooves 1157) formed by a regular or irregular pattern [0174].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the first surface of Liu in view of Liu 282 to comprise an irregular rough region to form a text on the first surface as taught by Moon [0174].
Regarding the limitation “and the rough region is formed after a portion of the epitaxial layer is removed,” this limitation is directed to a process and requires a product-by-process interpretation. Thus, claim 6 is limited only by the structure implied by the steps, and not the steps themselves. M.P.E.P. 2133 I.
Regarding claim 7, Liu does not teach the micro light-emitting diode according to claim 1, wherein the first surface comprises a rough portion and a platform portion, the platform portion surrounds a periphery of the rough portion, and the rough portion is recessed toward the second surface relative to the platform portion.
Moon, however, teaches a micro light-emitting diode (1050; fig. 19A) [0150] wherein a first surface (bottom surface, but is shown as vertically upward in fig. 15D) comprises a rough portion (grooves 1157; fig. 15D) [0174] and a platform portion (horizontal surface defined by 1152), the rough portion is recessed toward the second surface (top portion) relative to the platform portion (defined by 1152).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the first surface of Liu in view of Liu 282 to comprise an irregular rough region to form a text on the first surface as taught by Moon [0174].
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Chinese Pat. Pub. No. CN 110676355 A to He et al. (hereinafter “He”).
Regarding claim 14, Liu teaches a preparation method for a micro light-emitting diode, comprising:
forming an epitaxial layer (layers of light emitting unit 100; fig. 4) [0020] comprising a first semiconductor layer (semiconductor layer 111; fig. 4) [0021], an active layer (113; fig. 4) [0021], and a second semiconductor layer (semiconductor layer 112; fig. 4) [0021] arranged in sequence (the two semiconductor layer being disposed on both sides of the active layer), wherein the epitaxial layer (100) has a first surface (bottom surface in fig. 4) and a second surface (top surface in fig. 4) arranged opposite each other (on opposing sides), and the first semiconductor layer (111) is located on a side of the epitaxial layer (100) close to the first surface (bottom);
forming the epitaxial layer (100) from the second surface (upper) and forming a mesa (area of 111 in physical contact with electrode 121, hereinafter “mesa”), wherein the mesa (mesa) is exposed from the first semiconductor layer (111) and faces the second surface (top); and
forming a dielectric layer (protective layer 500 comprising silicon, silicon oxide, silicon nitride, or epoxy; fig. 4) [0034] covering the first surface (bottom) and extending from the first surface (bottom) to a side wall (lateral side) of the epitaxial layer (100), wherein a height H1 (distance 500 is in contact with 111) of the dielectric layer (500) on the side wall (lateral side) of the epitaxial layer (100) is less than a height of the mesa (height of 111 on the mesa side is greater than 500 on the sidewall).
Liu does not teach that the epitaxial layer is etched from the second surface to form the mesa.
He, however, teaches a preparation method for a micro light-emitting diode (fig. 1A-1K) comprising forming an epitaxial layer (layers of 110, 120, and 130; fig. 1L) through etching [0072] from a second surface (top surface) to form a mesa (portion of 130 on a lateral side of 110 and 120; fig. 1L).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the preparation method of Liu to etch the mesa to allow for the micro-LED to be formed in-situ, thus simplifying the process as taught by He [0072] (figs. 1H-1L).1
Claims 16, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Liu and further in view of U.S. Pat. Pub. No. US 20200373282 A1 to Liu et al. (hereinafter “Liu 282”).
Regarding claim 16, Liu teaches a micro light-emitting element (fig. 4), comprising:
a substrate (200; fig. 4) [0020];
at least one micro light-emitting diode (unit 100; fig. 4) [0020] arranged on the substrate (200), each of the micro light-emitting diode (100) comprising:
an epitaxial layer (layers of 100; fig. 4) [0020] comprising a first semiconductor layer (semiconductor layer 111; fig. 4) [0021], an active layer (113; fig. 4) [0021], and a second semiconductor layer (semiconductor layer 112; fig. 4) [0021] arranged in sequence (the two semiconductor layer being disposed on both sides of the active layer), wherein the epitaxial layer (layers of 100) has a first surface (bottom surface in fig. 4) and a second surface (top surface in fig. 4) arranged opposite each other (on opposing sides), the first semiconductor layer (111) is located on a side of the epitaxial layer (layers of 100) close to the first surface (bottom), the epitaxial layer (layers of 100) is configured with a mesa (area of 111 in physical contact with electrode 121, hereinafter “mesa”), the mesa (mesa) is exposed from the first semiconductor layer (111) and faces the second surface (top), and the first surface (bottom) faces (see fig. 4) or faces away from the substrate (200);
a dielectric layer (protective layer 500 comprising silicon, silicon oxide, silicon nitride, or epoxy; fig. 4) [0034] covering the first surface (bottom) and at least a portion of a side wall (lateral side) of the epitaxial layer (layers of 100), wherein a height H1 (distance 500 is in contact with 111) of the dielectric layer (500) on the side wall (lateral side) of the epitaxial layer (layers of 100) is less than a height of the mesa (mesa); and
an adhesive film (30; fig. 4) [0020] located between the substrate (200) and the micro light-emitting diode (unit 100).
Liu does not teach wherein a width of the adhesive film is less than a width of the epitaxial layer.
Liu 282, however, teaches micro-light emitting diodes (130a) wherein a width of the adhesive film (123; fig. 4) [0044] is less than a width of the epitaxial layer (131; fig. 4) [0038].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the micro light-emitting diodes to comprise an adhesive with a width which is less than a width of the epitaxial layer to allow for an encapsulant (anisotropic conductive film 120) to be disposed in the non-occupied space as taught by Liu 282 [0037].
Regarding claim 17, Liu in view of Liu 282 teaches the micro light-emitting element according to claim 16, wherein the substrate (200) comprises a transparent substrate (comprising a material such as sapphire) [0022], and the transparent substrate comprises a sapphire substrate [0022] or a glass substrate.
Regarding claim 20, Liu in view of Liu 282 does not teach a display, as presently modified, and according to Liu fig. 4, comprising a base having a driving circuit and at least one micro light-emitting diode arranged on the base according to claim 1, wherein the micro light-emitting diode is electrically connected to the driving circuit.
Liu, however, in the embodiment of fig. 5, teaches a display (fig. 5) comprising a base (board 400; fig. 5) [0036] having a driving circuit (circuit board) [0036] and at least one micro light-emitting diode (100; fig. 5) [0036] arranged on the base (400) according to claim 1, wherein the micro light-emitting diode (100) is electrically connected to the driving circuit (400) [0036].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the diode of Liu, fig. 4, to be connected to a circuit board with a driving circuit, as in Liu fig. 5, to allow for on and off control of the diode luminance as taught by Liu [0036].
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Liu 282 as applied to claim 16 above, and further in view of Moon.
Regarding claim 19, Liu in view Liu 282 do not teach the micro light-emitting element according to claim 16, wherein at least a partial region of the first surface is configured as a rough region formed by a regular or irregular pattern, and the rough region is formed after a portion of the epitaxial layer is removed.
Moon, however, teaches a micro light-emitting diode (1050; fig. 19A) [0150] wherein at least a partial region (region of 1157; fig. 15D) [0174] of the first surface (surface of 1157) is configured as a rough region (comprising grooves 1157) formed by a regular or irregular pattern [0174], and the rough region is formed after a portion of the epitaxial layer is removed (through etching) [0174].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the first surface of Liu in view of Liu 282 to comprise an irregular rough region to form a text on the first surface as taught by Moon [0174].
Allowable Subject Matter
13. Claims 2, 8-10, 13, 15, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, it is not found a reference which reasonably reads on the limitations of claim 2, or in other words, when combined with Liu, reads on the claim. The closest reference found is U.S. Pat. Pub. No. US 20220320400 A1 to Lopez et al. which teaches a close range of values for a thickness of dielectric layer, but this thickness is not measured on a sidewall of an epitaxial layer (see ¶ [0046]).
Regarding claim 8, it is not found a reference which reasonably reads on the limitations of claim 8, or in other words, when combined with Liu, reads on the claim. The closest reference found is U.S. Pat. Pub. No. US 20190189858 A1 to Li et al. but Li does not teach the limitation “wherein the first step exceeds the second step in a horizontal direction, and a width of the first step exceeding the second step is equal to the thickness D1 of the dielectric layer on the side wall of the epitaxial layer.” Claims 9-10 further comprise allowable subject matter only because of their dependence on claim 8.
Regarding claim 13, it is not found a reference which reasonably reads on the limitations of claim 13, or in other words, when combined with Liu, reads on the claim. The closest reference found is He which teaches an angled insulating layer but this angle is not measured from a sidewall (see fig. 3E wherein θ is measured on a top side).
Regarding claim 15, it not found a reference which reasonably reads on the limitations of claim 15, or in other words, when combined with Liu and He, reads on the claim. The closest reference, Moon, teaches a roughening process after the formation of a mesa, but does not teach that this process occurs before a dielectric layer is formed. Furthermore, Chinese Pat. Pub. No. CN 113328022 A to Wu teaches a dielectric layer formed over a roughened portion, but this is not done before the roughening portion is formed (Wu teaches that layer 40 is formed to protect underlying layers during an etch).
Regarding claim 18, it not found a reference which reasonably reads on the limitations of claim 18, or in other words, when combined with Liu, reads on the claim. Claim 18 comprises allowable subject matter for the same reason as claim 2.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN EDWARD CUTLER whose telephone number is (703)756-5415. The examiner can normally be reached Monday-Friday 7:30 am - 5:00 pm Eastern Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Drew Richards can be reached on (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ETHAN EDWARD CUTLER/Examiner, Art Unit 2892
/NORMAN D RICHARDS/ Supervisory Patent Examiner, Art Unit 2892
Prosecution Insights