DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 4-7, 9, 19-21 have been amended.
Claims 2, 3, 8, 10-14, 16, 18, and 22 have been cancelled.
Claims 1, 4-7, 9, 19-21 have been examined.
The specification, drawing, and claim objections in the previous Office Action have been addressed and are withdrawn, except as otherwise indicated below.
The § 112 rejections in the previous Office Action have been addressed and are withdrawn, except as otherwise indicated below.
Specification
The disclosure is objected to because of the following informalities.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Appropriate correction is required. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which Applicant may become aware in the specification.
Claim Interpretation
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. As indicated at MPEP § 2181, “module” and “unit” have both been held to be generic placeholders. Such claim limitations and corresponding structure from the specification, if any, are:
one or more processing modules … capable of implementing a vector operation method in claim 19—no corresponding structure disclosed.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 19 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 19 recites one or more processing modules capable of implementing a vector operation method. The disclosure does not provide adequate structure to perform the claimed function. The specification does not demonstrate that applicant has made an invention that achieves the claimed function because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention. This rejection could be overcome by changing module to circuit, or something similar.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 4-7, 9, 19-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the Applicant regards as the invention.
Claim 1 recites, at line 23, “reading the basic operation instruction. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this limitation is interpreted as, “reading the each basic operation instruction.” Claim 19 includes similar language and is similarly rejected.
Claim 19 recites one or more processing modules capable of implementing a vector operation method.. This limitation invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The specification is devoid of adequate structure to perform the claimed function. The specification does not provide sufficient details such that one of ordinary skill in the art would understand which structure or structures perform(s) the claimed function. Therefore, the claim is indefinite. This rejection could be overcome by changing module to circuit, or something similar.
Claims 4-7, 9, 20, and 21 are rejected as depending from rejected base claims and failing to cure the indefiniteness of those base claims.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 4-7, 9, 19-21 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claims recite splitting, generating, and executing, which fall within the “Mental Processes” grouping of abstract ideas as well as the “Mathematical Calculation” grouping of abstract ideas.
This judicial exception is not integrated into a practical application. The claimed additional elements, i.e., storing using registers and buffers, synchronous operations, compiling, format conversion, and ReLu operations, do not include:
Improvements to the functioning of a computer, or to any other technology or technical field - see MPEP 2106.05(a);
Applying the judicial exception with, or by use of, a particular machine - see MPEP 2106.05(b);
Effecting a transformation or reduction of a particular article to a different state or thing - see MPEP 2106.05(c); or
Applying or using the judicial exception in some other meaningful way beyond generally linking the use of the judicial exception to a particular technological environment, such that the claim as a whole is more than a drafting effort designed to monopolize the exception - see MPEP 2106.05(e).
The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements listed above are insufficient to amount to significantly more than the judicial exception. The elements amount to generic computing functions and/or generic computing components. Using a generic computer to perform the claimed activities is well-understood, routine, and conventional and represents insignificant extra-solution activity to the judicial exception. As such, claims 1, 4-7, 9, 19-21 are not patent-eligible.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-7, and 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 9,424,042 by Sasanka (hereinafter referred to as “Sasanka”) in view of US Publication No. 2021/0182077 by Chen et al. (hereinafter referred to as “Chen”) in view of US Publication No. 2008/0141012 by Yehia et al. (hereinafter referred to as “Yehia”).
Regarding claims 1, 19, and 20, taking claim 1 as representative, Sasanka discloses:
a … method, comprising: splitting a target vector operation to be performed to determine a plurality of basic operations in a predetermined execution order (Sasanka discloses, at col. 6, lines 25-38, splitting a vector multiple and add operation into a separate multiply operation and add operation, which discloses splitting a target vector operation into a plurality of basic operations to be performed in a predetermined order.);
sequentially generating, according to the predetermined execution order, a plurality of basic operation instructions corresponding to the plurality of basic operations (Sasanka discloses, at col. 6, lines 25-38, splitting a vector multiple and add operation into a separate multiply operation and add operation and executing the separate operations, which discloses generating corresponding instructions.); and
sequentially executing, according to the predetermined execution order, the plurality of basic operation instructions on initial data to be subjected to the target vector operation, so as to implement the target vector operation on the initial data (Sasanka discloses, at col. 6, lines 25-38, splitting a vector multiple and add operation into a separate multiply operation and add operation and executing the separate operations, which discloses sequentially executing the basic instructions in the predetermined order on initial data.),
wherein to-be-calculated data for a latter basic operation of two adjacent basic operations is an operation result of a former basic operation of the two adjacent basic operations (Sasanka discloses, at col. 6, lines 25-38, splitting a vector multiple and add operation into a separate multiply operation and add operation, which discloses the result of the former operation is used in the latter operation.),
sequentially generating, according to the predetermined execution order, the plurality of basic operation instructions corresponding to the plurality of basic operations comprises: storing the generated basic operation instructions … after each basic operation instruction is generated (Sasanka discloses, at col. 8, lines 25-32, translating instructions. Storing the instructions after they are generated is implicit.),
sequentially executing, according to the predetermined execution order, the plurality of basic operation instructions on the initial data to be subjected to the target vector operation so as to implement the target vector operation on the initial data comprises: for execution of each basic operation instruction, reading the basic operation instruction … (Sasanka discloses, at col. 8, lines 25-32, translating instructions and using the translated instructions. Reading the translated instructions is implicit.); and
performing an operation on the to-be-calculated data according to the read basic operation instruction (Sasanka discloses, at col. 6, lines 25-38, splitting a vector multiple and add operation into a separate multiply operation and add operation, which discloses performing an operation on the data according to the basic operation instruction.); and
an operation of generating an ith basic operation instruction and an operation of executing a jth basic operation instruction are performed …, wherein both i and j denote sequence numbers and are positive integers, and i > j (Sasanka discloses, at Figure 4, a pipeline that includes a translating stage, i.e., generating, and an execution stage, which discloses generating and executing instructions in a sequence.).
Sasanka does not explicitly disclose the aforementioned method is neural network accelerating, the aforementioned storing is in a register, the aforementioned reading is from the register, the aforementioned performing is synchronously.
However, in the same field of endeavor (e.g., processing) Chen discloses:
a neural network accelerator (Chen discloses, at Figure 51C and related description, a neural network accelerator.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Sasanka to include neural network acceleration, as disclosed by Chen, in order to improve flexibility by ensuring adaptability to neural networking applications, which are becoming more and more common and significant in processing.
Also in the same field of endeavor (e.g., processing) Yehia discloses:
storing to and reading from storage for translated instructions (Yehia discloses, at Figure 1 and related description, microcode cache, which discloses a register.); and
synchronous operations (Yehia discloses, at Figure 5 and related description, a pipelined processor, which discloses stages operating concurrently or synchronously.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Sasanka to include the register and synchronous operations disclosed by Yehia in order to realize the well-known performance improvements represented by pipelined processing, e.g., higher throughput.
Regarding claim 4, Sasanka discloses the elements of claim 1, as discussed above. Sasanka also discloses:
wherein before splitting the target vector operation to be performed to determine the plurality of basic operations in the predetermined execution order, the vector operation method further comprises: writing the initial data to a buffer to be used as the to-be-calculated data for a first basic operation (Sasanka discloses, at col. 8, lines 58-61, receiving input from memory, which discloses prior writing the data to a buffer.),
before performing a last basic operation, execution of each basic operation instruction further comprises: storing an operation result in the buffer to be used as the to-be-calculated data for a next basic operation (Sasanka discloses, at col. 8, line 58-col. 9, line 13, storing results in a memory.), and
before performing the operation on the to-be-calculated data according to the read basic operation instruction, execution of each basic operation instruction further comprises: reading the to-be-calculated data from the buffer (Sasanka discloses, at col. 8, lines 58-61, receiving input from memory, which discloses reading the buffer.).
Regarding claim 5, Sasanka discloses the elements of claim 4, as discussed above. Sasanka also discloses:
wherein sequentially generating, according to the predetermined execution order, the plurality of basic operation instructions corresponding to the plurality of the basic operations comprises: sequentially generating a plurality of initial operation instructions according to the plurality of basic operations, wherein the eachgenerated initial operation instruction is written to a second register after each initial operation instruction is generated (Sasanka discloses, at col. 7, line 51-col. 8, line 32, translating at compile time, which discloses generating initial operation instructions and writing the initial operation instructions to a second register.);
sequentially reading the initial operation instruction from the second register (Sasanka discloses, at col. 7, line 51-col. 8, line 32, compiling the translated instructions, which discloses reading the initial operation instructions.); and
respectively compiling each initial operation instruction to obtain each corresponding basic operation instruction (Sasanka discloses, at col. 7, line 51-col. 8, line 32, compiling the translated instructions.).
Regarding claim 6, Sasanka discloses the elements of claim 5, as discussed above. Sasanka also discloses:
the first register and the second register are both pipeline registers (Sasanka discloses, at Figure 1 and related description, registers, which discloses reading first and second pipeline registers.).
Regarding claim 7, Sasanka discloses the elements of claim 4, as discussed above. Sasanka also discloses:
the initial data is in a predetermined format, and before sequentially executing, according to the predetermined execution order, the plurality of the basic operation instructions on the initial data to be subjected to the target vector operation so as to implement the target vector operation on the initial data, the vector operation method further comprises: acquiring input data (Sasanka discloses, at col. 8, lines 58-61, receiving input from memory, which discloses acquiring input data having and the initial data having a predetermined format.); and
converting the input data into the initial data in the predetermined format (Sasanka discloses, at col. 4, lines 52-55, translating between vector widths, which discloses converting input data into the initial data in the predetermined format.).
Regarding claim 21, Sasanka discloses the elements of claim 1, as discussed above. Sasanka also discloses:
wherein for different initial data, the operation of sequentially executing, according to the predetermined execution order, the plurality of basic operation instructions on the initial data to be subjected to the target vector operation so as to implement the target vector operation on the initial data is performed concurrently (Sasanka discloses, at col. 3, lines 40-42, a SIMD implementation, which discloses concurrent execution.).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Sasanka in view of Chen in view of Yehia in view of US Publication No. 2022/0129755 by Keller et al. (hereinafter referred to as “Keller”).
Regarding claim 9, Sasanka, as modified, discloses the elements of claim 1, as discussed above. Sasanka does not explicitly disclose the target vector operation comprises a ReLU activation operation, and the initial data is matrix data, in the operation of splitting the target vector operation to be performed to determine the plurality of basic operations in the predetermined execution order, the basic operations in the predetermined execution order are respectively: a size-comparison basic operation, wherein the initial data is compared with a reference matrix to obtain maximum values, a feature map of the reference matrix is the same as a feature map of the initial data, and each element of the reference matrix is 0; and a multiplication basic operation, wherein each element point of the to-be- calculated data is multiplied by a coefficient K.
However, in the same field of endeavor (e.g., processing) Chen discloses:
a ReLU activation operation, and the initial data is matrix data (Chen discloses, at ¶ [1887], a ReLu operation. As disclosed at Figure 1C and related description, initial data is matrix data.),
in the operation of splitting the target vector operation to be performed to determine the plurality of basic operations in the predetermined execution order, the basic operations in the predetermined execution order are respectively: a size-comparison basic operation, wherein the initial data is compared with a reference matrix to obtain maximum values, a feature map of the reference matrix is the same as a feature map of the initial data (Chen discloses, at ¶ [1791] a size comparison unit, which disclose size comparison basic operation comparing initial data and a reference matrix to obtain maximum values and a feature map of the reference matrix is the same as that of the initial data.), and
…a multiplication basic operation, wherein each element point of the to-be- calculated data is multiplied by a coefficient K (Chen discloses, at Figure 1A and related description, matrix multiplication, which discloses multiplying each element by a coefficient K.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Sasanka to include ReLu, size comparison, and multiplication operations for matrix data because these are commonly used operations in neural networks and including such functionality increases the utility and value of Sasanka’s system.
Also in the same field of endeavor (e.g., processing) Chen discloses:
a zero matrix (Keller discloses, at ¶ [0130], a zero matrix.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Sasanka to include zero matrices, as disclosed by Keller, because doing so is a useful technique for initializing matrices.
Response to Arguments
On page 11 of the response filed September 11, 2025 (“response”), the Applicant argues, “The subject matter of claims 1, 4-7 and 9 is amended as "neural network accelerating method", and all limitations of the originally filed claims 2 and 3 are combined into the independent claim 1 to include improvements to the function of a computer.”
Though fully considered, the Examiner respectfully disagrees. The Applicant has not indicated the manner in which the claimed method purportedly improves the functionality of a computer. The Examiner maintains that various elements requiring computer components are merely generic implementation details. Rather than reciting improvements the functioning of a computer, the claims recite implementing the claimed method on a computer, which is not significantly more than the abstract ideas. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On pages 14-15 of the response the Applicant argues, “According to the above paragraphs, only instruction translation is disclosed, and the instruction processing apparatus 415 may include a register, however, Sasanka does not mention storing the translated instruction in the register, let along that "storing the14 generated basic operation instructions in a first register after each basic operation instruction is generated".”
Though fully considered, the Examiner respectfully disagrees. Translating instructions involves generating translations. The translations are implicitly stored. However, based on the claim amendments presented in the response, the Examiner has clarified that the storing is in a register, as taught by Yehia’s microcode cache. See, e.g., Yehia at Figure 1 and related description.
On page 16 of the response the Applicant argues, “what is shown in Fig. 4 is only a block diagram of the instruction processing apparatus 415, not a pipeline diagram recognized by the Examiner. It should be recognized that the arrows between modules (blocks) shown in Fig. 4 are only used to indicate the direction of data (information) transfer between modules. Therefore, Sasanka does not record that "the operation of generating the ith basic operation instruction and the operation of executing the jth basic operation instruction are performed synchronously".”
Though fully considered, the Examiner respectfully disagrees. Sasanka explicitly discloses that the embodiments can be implemented using pipelined processors. See, e.g., col. 15, lines 38-41. However, based on the claim amendments presented in the response, the Examiner has clarified that the operations are performed in a pipelined processor, as taught by Yehia. See, e.g., Yehia at Figure 5 and related description. Pipelined operations mean that each stage is active at the same time, which discloses the limitations in question.
On page 16 of the response the Applicant argues, “the "parallel execution" recorded in US20100312988A1 is a parallel operation between multiple processing lanes, not between the operations of generating a basic operation instruction and executing a basic operation instruction. It should be recognized that the parallel execution between the operations of generating a basic operation instruction and executing a basic operation instruction is actually a parallel execution within one data channel.”
Though fully considered, the Examiner respectfully disagrees. As the reference in question is cited as pertinent, rather than actually applied in a rejection, the Applicant’s arguments are moot.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure.
US 20170286110 by Agron discloses an instruction cache prior to a decode unit in a pipeline and instruction translation.
US 20160098277 by Day discloses a translated instruction queue.
US 20190377580 by Vorbach discloses pipeline registers.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/
Primary Examiner, Art Unit 2183