DETAILED ACTION
This action is responsive to the following communications: the Application filed on November 25, 2024, the Foreign Priority papers retrieved on December 9, 2021, and the Information Disclosure Statement filed on June 6, 2024.
Claims 1-15 are pending. Claims 1 and 13 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on June 6, 2024. This IDS has been considered.
Drawings
The drawings are objected to because all of the Figures filed on November 25, 2024 are degraded, showing dotted lines and dotted lettering and numbering, which may indicate applicant submitted Figures that were in greyscale. Applicant is reminded that solid lines used in the Drawings must be uniformly thick, black, and solid and the words and labels in the Drawings must be plain and legible. MPEP 608.02(f)(V).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 11 and 15 are objected to because of the following informalities:
In claim 11, line 1, “wherein he increment value kN” should be --wherein the increment value kN--.
In claim 15, line 7, “Incrementing the counter k by the increment value kN.;” should be --Incrementing the counter k by the increment value kN;--.
In claim 15, line 10, “following step E.,” should be --following step E,--.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
In claim 1, the claim recites “a logic block for preventing the hammer effect which comprises counting means implementing m hammer counters”. Because the claim uses the term “means” and recites the function of implementing hammer counters and incrementing a count value according to a timing dependent increment, the limitation is interpreted under 35 U.S.C. 112(f).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to independent claim 1, the claim recites “n memory rows, referred to as row i for i ranging from 1 to n, each row i being liable to effect a row hammer having a range p on one or more rows j, said to be within the hammering range of row i, with j ranging from i+1 to i+p and from i-1 to i-p”. This limitation renders the scope of the claim unclear because for boundary rows of the memory bank, the recited range includes row indices that do not exist within the memory bank. For example, when i=1 and p is greater than or equal to 0, the claimed range “i-1 to i-p” includes row indices less than 1, although the claim defines rows only from 1 to n. Similarly, when i=n, the claimed range “i+1 to i+p” includes row indices greater than n. Thus, it is unclear whether the claimed “rows j” include only existing rows within the memory bank, whether boundary rows are excluded from the limitation, or whether some other addressing scheme is intended.
Claim 1 further recites “m hammer counters, called counters k, k ranging from 1 to m”, but then recites “a count k by an increment value kN”. Because k is already defined as the counter index, it is unclear whether “count k” refers to the kth counters, the value stored in the kth counter, or a separate count variable. Thus, the metes and bounds of the claimed counter limitation are unclear.
Claim 1 also recites “refresh one or more rows as soon as a count k of one of the associated counters k reaches a threshold value M”. That limitation does not clearly define the required timing of the claimed refresh operation. It is unclear whether “as soon as” requires immediate refresh, refresh within a clock cycle, refresh before a next activation, or refresh in response to the threshold being reached. The specification also indicates that counter incrementation may occur after activation or after a subsequent preload, and that delay effects may be considered in determining the threshold value M, further confirming that the timing relationship is not clearly bounded.
For the above reasons, claim 1 does not clearly define the scope of the claimed invention and is rejected under 35 U.S.C. 112(b). Claims 2-12 are rejected as indefinite for depending from and incorporating the indefinite limitations of claim 1.
With respect to claim 3, the claim recites “the count k is incremented by the increment value kN only after the end of the preload PN+1 of the activation cycle N+1 immediately following the activation AN of the activation cycle N”. This limitation is unclear in view of claim 1, which recites incrementing the count “after the end of each activation cycle N”. It is unclear whether the increment for activation cycle N occurs after activation cycle N, during activation cycle N+1, after preload PN+1, or after completion of activation cycle N+1. Thus, the timing relationship between the claimed activation cycle, preload, and counter increment is unclear.
With respect to claim 6, the claim recites “one DRAM memory bank forms a memory bank divided into p sub-banks, each sub-bank h, for h ranging from 1 to p” and “the number m of counters k is equal to the number p of sub-banks h”, while the claim 1 introduces p as the hammering range of a row. It is unclear whether the number of sub-banks must be the same as the hammering range p recited in claim 1, or whether p in claim 6 is intended to represent a different variable. Therefore, the scope of claim 6 is unclear.
With respect to claim 7, the claim recites “the counter k associated with a sub-bank h”, but then recites “said sub-bank k”. The phrase “said sub-bank k” lacks antecedent basis. It is unclear whether “said sub-bank k” refers to the previously recited sub-bank h, the kth counter or another sub-bank indexed by k.
With respect to claim 9, the claim recites “reset or decrement the counter k as soon as the row, or one of the rows, associated with this counter has been refreshed”. Claim 9 depends from claim 8. Claim 8 requires that “each counter k, for k ranging from 1 to n, is associated with a row i, for i ranging from 1 to n, which is its own”. Because claim 8 requires one row per counter, while claim 9 refers to “one of the rows” associated with the counter, it is unclear whether the counter is associated with one row or multiple rows.
With respect to claim 11, the claim recites “activation N-1 and activation N”. However, claim 1 defines “an activation cycle N comprising an activation AN”. Claim 1 does not define “activation N-1” or “activation N”. Therefore, it is unclear whether “activation N” refers to activation cycle N, activation AN, or another activation event.
With respect to claim 12, the claim recites “the determination of the first value and second value”. However, claim 11 recites “a first increment value and a second increment value”, not a “first value” and “second value”. Therefore, “the first value and second value” lack clear antecedent basis. Claim 12 further recites “the determination of the first value and second value involves a first table and a second table, respectively”. The word “involves” does not clearly define the relationship between the tables and the claimed values. It is unclear whether the first and second tables store the values, are used to calculate the values, contain lookup entries for determining the values, or participate in some other unspecified manner.
With respect to independent claim 13, the claim recites “a method for preventing the memory row hammer effect of a DRAM device”, but the method claim uses several variables and structural limitations without clear antecedent basis. Claim 13 does not clearly define “an activation cycle N”, “an activation AN”, “a preload PN”, “the duration TAN”, “the duration TPN”, “rows j”, or the hammering range. Thus, the scope of the method is unclear.
Claim 13 further recites method subject matter but uses apparatus style language, including: “m hammer counters….is configured to increment…; a row refresh logic block configured to refresh…”. It is unclear whether claim 13 is directed to method steps performed by the algorithm, or to apparatus components configured to perform functions. The claim should recite active method steps such as “incrementing” and “refreshing”, rather than structural components “configured to” perform those functions.
Claim 13 also recites “m hammer counters, called counters k, k ranging from 1 to m”, but then recites “a count k by an increment value kN”. Because k is already defined as the counter index, it is unclear whether “count k” refers to the kth counters, the value stored in the kth counter, or a separate count variable. Thus, the metes and bounds of the claimed counter limitation are unclear.
For the above reasons, claim 13 does not clearly define the scope of the claimed invention and is rejected under 35 U.S.C. 112(b). Claims 14-15 are rejected as indefinite for depending from and incorporating the indefinite limitations of claim 13.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5, 8, 10 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Pan (US 20220165347) in view of Ayyapureddi et al. (US 20210057012).
Regarding independent claim 1, Pan discloses a DRAM memory device [Fig. 1, para. 18] which comprises:
- at least one DRAM memory bank [see Fig. 1, the memory array 118 is shown as including sixteen memory banks BANK0-BANK15, para. 19] provided with n memory rows, referred to as row i for i ranging from 1 to n [see Fig. 1, each memory bank includes a plurality of word lines WL, para. 19], each row i being liable to effect a row hammer having a range p on one or more rows j, said to be within the hammering range of row i, with j ranging from i+1 to i+p and from i-1 to i-p [see Fig. 3, the refresh address generator 350 may determine the locations of one or more victim rows based on the match address HitXADD. The victim rows may include rows which are physically adjacent to the aggressor row or rows (e.g., HitXADD+1 and HitXADD−1), para. 64], each row i being configured to have activation cycles N imposed on it continuously [see Fig. 3, the DRAM interface 340 provides a row address XADD, the auto-refresh signal AREF, an activation signal ACT, and a precharge signal Pre, where the activation signal ACT is provided to activate a given bank of the memory and the precharge signal Pre is provided to precharge the given bank of the memory, para. 55. Responsive to the activation signal ACT and the row address XADD (and IREF and RHR being inactive), the row decoder 308 directs one or more access operations, para. 66], an activation cycle N comprising an activation AN, of duration TAN, and a preload PN, of duration TPN, preceding the activation AN [an activation signal ACT, and a precharge signal Pre, para. 55. The timer circuit 458 measures a length of time the activation signal ACT is active, para. 72. Waiting for the precharge command may increase the row precharge time (tRP) of the memory because time must be provided after the precharge command for writing the updated count values back to the count value memory cells, para. 79];
- a logic block for preventing the hammer effect which comprises counting means implementing m hammer counters, called counters k, k ranging from 1 to m [see Fig. 4, the count control circuit 428 includes a count value register 452, a threshold comparator 454, a count update circuit 456, a timer circuit 458, a count inference circuit 460, and optionally, an error correction circuit 462. The count value memory cells 426 may implement one or more counters Counter0-CounterN, para. 67-68], each k counter being associated with one or more of the rows i [count value memory cells for a word line implement counters and those count values represent the number of times and length of time that word line has been accessed, para. 68-69], and is configured to increment, after the end of each activation cycle N of one or more of the rows i with which it is associated, a count k by an increment value kN [the count update circuit 456 updates the value of the count including incrementing or decrementing that count value, para. 71. Responsive to activation of a word line, the count control circuit determines an access count value and updates the counters; while the word line remains activated, the count control circuit updates the count value and writes it back to one of the counters, para. 82-83], the increment value kN being a function of the duration TAN [the count control circuit may further update the count value for the word line responsive to a length of time the word line remains activated, para. 83], the increment value kN quantifying the hammer effect from the one or more of the rows i on rows j within hammering range [Pan teaches the apparatuses and methods disclosed herein provide a deterministic technique for detecting various memory attacks, such as row hammer and clobber attacks and allow for tracking a number of activations and/or time of activation of word lines., para. 103];
- a row refresh logic block configured to refresh one or more rows as soon as a count k of one of the associated counters k reaches a threshold value M [the threshold comparator 454 compares the count value to a threshold value and activate an aggressor row detection signal RHR_TRIG signal if a count value is equal to or greater than the threshold value. The active RHR_TRIG signal may cause the refresh control circuit to latch a current row address and/or trigger a targeted refresh operation, para. 70], the threshold value M being chosen to prevent the row hammer effect [the threshold values such as 100, 500, 1,000, 2,000, and/or 5,000 accesses and/or equivalent activation time, which are used for detecting various memory attacks, such as row hammer and clobber attacks, para. 92 and 103].
However, Pan is silent with respect to the increment value kN being a decreasing function of the duration TPN.
Ayyapureddi et al. teach an analog accumulator for determining row access rate. Ayyapureddi et al. disclose responsive to a row address match, a preset amount of charge is added to a capacitor, increasing a voltage HammerFreq provided by the accumulator circuit. The voltage HammerFreq decreases over time (e.g., due to the ‘leak’ through the transistor 564 of FIG. 5) [para. 98]. Ayyapureddi et al. also disclose the voltage HammerFreq may be increased each time an activation of the signal Match is received and may otherwise decrease steadily over time. Thus, the more rapidly that activations of the signal Match are received, the higher the voltage HammerFreq may become [para. 80].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Ayyapureddi et al. to the teachings of Pan such that modifying Pan’s row hammer detection system to include the time decaying access rate accumulator of Ayyapureddi et al. because both references are directed to identifying aggressor rows and performing refresh operation to prevent data loss from row hammer. Thereby, that modification would have predictably improved row hammer protection by causing rapidly repeated activations to contribute more strongly to the hammer count while allowing longer preload intervals to reduce the effective hammer contribution.
Regarding claim 2, Pan in combination with Ayyapureddi et al. teach the limitations with respect to claim 1.
Furthermore, Pan discloses wherein the increment value kN is an increasing function of the time TAN [the count control circuit may further update the count value for the word line responsive to a length of time the word line remains activated. If the word line remains activated for additional periods, the count control circuit continues to increment the count value for the word line, para. 83].
Regarding claim 5, Pan in combination with Ayyapureddi et al. teach the limitations with respect to claim 1.
Furthermore, Pan discloses wherein the logic block for preventing the row hammer effect is configured to measure, for each activation cycle N, the duration TAN of each activation AN, and the duration TPN of each preload PN [the timer circuit 458 measures a length of time the activation signal ACT is active, para. 72. Waiting for the precharge command may increase the row precharge time (tRP) of the memory because time must be provided after the precharge command for writing the updated count values back to the count value memory cells, para. 79].
Regarding claim 8, Pan in combination with Ayyapureddi et al. teach the limitations with respect to claim 1.
Furthermore, Pan discloses wherein the number m of counters k is equal to the number n of memory rows, so that each counter k, for k ranging from 1 to n, is associated with a row i, for i ranging from 1 to n, which is its own [each word line WL may have a number of count value memory cells 226 based on an expected maximum value of an access count that may need to be stored in the count value memory cells 226, para. 52. The count value memory cells may implement a single counter, para. 79].
Regarding claim 10, Pan in combination with Ayyapureddi et al. teach the limitations with respect to claim 1.
Furthermore, Pan discloses wherein the refresh logic block is also configured to perform periodic refreshes of the memory row set at regular time intervals [the device 100 may be periodically placed in a refresh mode. Thus, refresh operations may be performed periodically each time the memory device is in the refresh mode, para. 32. The DRAM interface 340 provides the auto-refresh signal AREF that is a periodic signal which may indicate when an auto-refresh operation is to occur, para. 55].
Regarding independent claim 13, Pan discloses a method for preventing the memory row hammer effect of a DRAM device [para. 103], the DRAM device comprising at least one DRAM memory bank [see Fig. 1, the memory array 118 is shown as including sixteen memory banks BANK0-BANK15, para. 19] provided with n memory rows called row i for i ranging from 1 to n [see Fig. 1, each memory bank includes a plurality of word lines WL, para. 19], the method comprising the implementation of an algorithm for preventing the row hammer effect, said algorithm implementing:
- m hammer counters, called counters k, k ranging from 1 to m [see Fig. 4, the count control circuit 428 includes a count value register 452, a threshold comparator 454, a count update circuit 456, a timer circuit 458, a count inference circuit 460, and optionally, an error correction circuit 462. The count value memory cells 426 may implement one or more counters Counter0-CounterN, para. 67-68], each k counter being associated with one or more of the rows i [count value memory cells for a word line implement counters and those count values represent the number of times and length of time that word line has been accessed, para. 68-69], and is configured to increment, after the end of each activation cycle N of one or more of the rows i with which it is associated, a count k by an increment value kN [the count update circuit 456 updates the value of the count including incrementing or decrementing that count value, para. 71. Responsive to activation of a word line, the count control circuit determines an access count value and updates the counters; while the word line remains activated, the count control circuit updates the count value and writes it back to one of the counters, para. 82-83], the increment value kN being a function of the duration TAN [the count control circuit may further update the count value for the word line responsive to a length of time the word line remains activated, para. 83], the increment value kN quantifying the hammer effect from the one or more of the rows i on rows j within hammering range [Pan teaches the apparatuses and methods disclosed herein provide a deterministic technique for detecting various memory attacks, such as row hammer and clobber attacks and allow for tracking a number of activations and/or time of activation of word lines., para. 103];
- a row refresh logic block configured to refresh one or more rows as soon as a count k of one of the associated counters k reaches a threshold value M [the threshold comparator 454 compares the count value to a threshold value and activate an aggressor row detection signal RHR_TRIG signal if a count value is equal to or greater than the threshold value. The active RHR_TRIG signal may cause the refresh control circuit to latch a current row address and/or trigger a targeted refresh operation, para. 70], the threshold value M being chosen to prevent the row hammer effect [the threshold values such as 100, 500, 1,000, 2,000, and/or 5,000 accesses and/or equivalent activation time, which are used for detecting various memory attacks, such as row hammer and clobber attacks, para. 92 and 103].
However, Pan is silent with respect to the increment value kN being a decreasing function of the duration TPN.
Ayyapureddi et al. teach an analog accumulator for determining row access rate. Ayyapureddi et al. disclose responsive to a row address match, a preset amount of charge is added to a capacitor, increasing a voltage HammerFreq provided by the accumulator circuit. The voltage HammerFreq decreases over time (e.g., due to the ‘leak’ through the transistor 564 of FIG. 5) [para. 98]. Ayyapureddi et al. also disclose the voltage HammerFreq may be increased each time an activation of the signal Match is received and may otherwise decrease steadily over time. Thus, the more rapidly that activations of the signal Match are received, the higher the voltage HammerFreq may become [para. 80].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Ayyapureddi et al. to the teachings of Pan such that modifying Pan’s row hammer detection system to include the time decaying access rate accumulator of Ayyapureddi et al. because both references are directed to identifying aggressor rows and performing refresh operation to prevent data loss from row hammer. Thereby, that modification would have predictably improved row hammer protection by causing rapidly repeated activations to contribute more strongly to the hammer count while allowing longer preload intervals to reduce the effective hammer contribution.
Regarding claim 14, Pan in combination with Ayyapureddi et al. teach the limitations with respect to claim 13.
Furthermore, Pan discloses wherein the increment value kN is an increasing function of the duration TAN [the count control circuit may further update the count value for the word line responsive to a length of time the word line remains activated. If the word line remains activated for additional periods, the count control circuit continues to increment the count value for the word line, para. 83].
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Pan (US 20220165347) in view of Ayyapureddi et al. (US 20210057012) as applied to claim 1 above and further in view of Devaux et al. (US 10885966).
Regarding claim 4, Pan in combination with Ayyapureddi et al. teach the limitations with respect to claim 1.
However, Pan in combination with Ayyapureddi et al. are silent with respect to wherein the set of counters k are saved in at least one table.
Devaux et al. teach an algorithm for preventing the row hammer effect which implements the use of a table [col. 1, lines 33-34 and col. 6, lines 50-55].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Devaux et al. to the teachings of Pan in combination with Ayyapureddi et al. such that storing Pan’s set of counters in at least one table as taught by Devaux et al., because table was a known implementation for row hammer prevention algorithms and would provide an organized memory structure for associating counter values with rows.
Conclusion
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/DUY H LUONG/Examiner, Art Unit 2825
/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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