Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on September 24th, 2024, was filed prior to the mailing date of the first office action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1 rejected on the ground of nonstatutory double patenting as being unpatentable over Claim 1 of U.S. Patent No. 12,107,111 in view of Claim 4 of 12,107,111.
Claimed Invention
U.S. Patent 12,107,111
an infrared detector based on a CMOS process, comprising: a CMOS measuring circuit system and a CMOS infrared sensing structure, wherein both the CMOS measuring circuit system and the CMOS infrared sensing structure are fabricated using the CMOS process, and wherein the CMOS infrared sensing structure is directly fabricated on the CMOS measuring circuit system;
An infrared detector with a multi-layer structure based on a CMOS process, comprising: a CMOS measuring circuit system and a CMOS infrared sensing structure, wherein both the CMOS measuring circuit system and the CMOS infrared sensing structure are fabricated by using CMOS technology, and wherein the CMOS infrared sensing structure is directly fabricated on the CMOS measuring circuit system;
wherein the CMOS infrared sensing structure includes at least one sealed release isolation layer above the CMOS measuring circuit system, wherein the sealed release isolation layer is configured to protect the CMOS measuring circuit system from process influence during an etching course for fabricating the CMOS infrared sensing structure;
wherein at least one sealed release isolation layer is arranged above the CMOS measuring circuit system, and the sealed release isolation layer is configured to protect the CMOS measuring circuit system from process influence in a release etching course of manufacturing the CMOS infrared sensing structure;
wherein the CMOS infrared sensing structure comprises at least two metal interconnect layers, at least two dielectric layers and a plurality of interconnect through holes, the dielectric layer comprises at least one sacrificial layer and one thermal-sensitive dielectric layer, wherein the metal interconnect layer comprises at least a reflecting layer and an electrode layer;
wherein the CMOS manufacturing process for the CMOS infrared sensing structure comprises a metal interconnection process, a through hole process, an IMD process, and an RDL process, wherein the CMOS infrared sensing structure comprises at least three metal interconnection layers, at least three dielectric layers and a plurality of interconnection through holes, wherein the at least three metal interconnection layer comprises at least a reflecting layer and two electrode layers, and wherein the dielectric layer comprises at least two sacrificial layers and a heat-sensitive dielectric layer;
wherein the thermal-sensitive dielectric layer comprises a thermal-sensitive material with a temperature coefficient of resistance greater than a predetermined value, wherein the thermal-sensitive dielectric layer is configured to convert a temperature change corresponding to infrared radiation absorbed by the thermal-sensitive dielectric layer into a resistance change, and then convert an infrared signal into an electrically readable signal by the CMOS measuring circuit system, wherein the infrared signal corresponds to the resistance change;
wherein the heat-sensitive dielectric layer is configured to convert a temperature change corresponding to infrared radiation absorbed by the heat-sensitive dielectric layer into a resistance change, and then convert an infrared target signal into a signal which is electrically readable through the CMOS measuring circuit system;
wherein the CMOS infrared sensing structure comprises a resonant cavity formed by the reflecting layer and the thermal-sensitive dielectric layer, a suspended micro-bridge structure for controlling heat transfer, and a columnar structure with electrical connection and supporting functions,
wherein the CMOS infrared sensing structure comprises a resonant cavity composed of the reflecting layer and the heat-sensitive dielectric layer and a suspended micro-bridge structure for controlling heat transfer, wherein the suspended micro-bridge structure comprises at least one layer of beam structure and at least one layer of absorption plate, the beam structure is located at one side of the absorption plate close to or away from the CMOS measuring circuit system, a first columnar structure is provided between the reflecting layer and the beam structure, wherein the first columnar structure is directly electrically connected to a support base in the reflecting layer and the corresponding beam structure, wherein the beam structure is electrically connected to the CMOS measuring circuit system through the first columnar structure and the support base, wherein a second columnar structure is provided between the absorption plate and the beam structure, wherein the second columnar structure is directly electrically connected to the corresponding absorption plate and the corresponding beam structure, and wherein the absorption plate is configured to convert an infrared signal into an electrical signal and electrically connect to the corresponding first columnar structure through the second columnar structure and the corresponding beam structure; wherein the first columnar structure comprises at least one layer of solid columnar structure and/or at least one layer of hollow columnar structure, wherein the second columnar structure comprises at least one of a layer of solid columnar structure or a layer of hollow columnar structure; wherein at least one hole-shaped structure is formed in the absorption plate, and the hole- shaped structure at least penetrates through a dielectric layer in the absorption plate; and/or, at least one hole-shaped structure is formed in the beam structure;
wherein the CMOS measuring circuit system is configured to measure and process a value of an array resistor formed by one or more CMOS infrared sensing structures and convert the infrared signal corresponding to the value of the array resistor into an image electrical signal.
wherein the CMOS measuring circuit system is configured to measure and process a value of an array resistor formed by one or more CMOS infrared sensing structures, and convert the infrared signal into an image electrical signal; wherein the CMOS measuring circuit system comprises a bias generation circuit, a column-level analog front-end circuit, and a row-level circuit; wherein an input end of the bias generation circuit is connected to an output end of the row-level circuit, wherein an input end of the column-level analog front-end circuit is connected to an output end of the bias generation circuit, wherein the row-level circuit comprises a row-level mirror pixel and a row selection switch, wherein the column-level analog front-end circuit comprises a blind pixel; wherein the row-level circuit is distributed in each pixel and selects a signal to-be-processed according to a row strobe signal of a time sequence generation circuit, and outputs a current signal to the column-level analog front-end circuit to perform current and voltage conversion output under the action of the bias generation circuit; and wherein the row-level circuit outputs a third bias voltage to the bias generation circuit when the row-level circuit is strobed by the control of the row selection switch, wherein the bias generation circuit outputs a first bias voltage and a second bias voltage according to an input constant voltage and the third bias voltage, wherein the column-level analog front-end circuit obtains two paths of currents according to the first bias voltage and the second bias voltage, and performs transimpedance amplification on a difference between the generated two paths of currents and outputs the difference as an output voltage.
Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations of the claimed invention wherein “at least two metal interconnect layers”, “at least two dielectric layers”, “at least one sacrificial layer”, and “an electrode layer” are anticipated by the limitations of 12,107,111 in Claim 1 wherein “at least three metal interconnect layers”, “at least three dielectric layers”, “at least two sacrificial layers”, and “two electrode layers”.
Additionally, the limitation of the claimed invention wherein “a thermal-sensitive material with a temperature coefficient of resistance greater than a predetermined value” overlaps with the limitations of 12,107,111 in Claim 4 wherein “at least one of materials with temperature coefficient of resistance larger than a set value”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the dielectric layer" in line 13. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the limitation will be interpreted as “the at least two dielectric layers”.
Claim 1 recites the limitation "the metal interconnect layer" in lines 14-15. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the limitation will be interpreted as “the at least two metal interconnect layers”.
Claim 2 recites the limitation "the metal interconnection layer" in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the limitation will be interpreted as “a metal interconnection layer”.
Claim 6 recites the limitation "a metal interconnection layer " in line 12. It is unclear if the metal interconnection layer is the same as the one defined in lines 5-6 or a second, different one. For the purpose of examination, the limitation will be interpreted as “a second metal interconnection layer”.
Claim 6 recites the limitation "the metal interconnection process and the interconnect via process" in lines 13-14. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the limitation will be interpreted as “the metal interconnection process and the interconnect via process”.
Claim 6 recites the limitation "the thermal-sensitive dielectric layer" in line 16. It is unclear if the thermal-sensitive dielectric layer is the same as the one defined in line 14 of Claim 1 or the one defined in line 6 of Claim 6. For the purpose of examination, the limitation will be interpreted as “the at least one thermal-sensitive dielectric layer”.
Claim 9 recites the limitation "the metal interconnection layer " in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the limitation will be interpreted as “the at least two metal interconnect layers”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate that the corresponding limitations are addressed with a secondary reference/embodiment in an obviousness analysis.
Claims 1-9 rejected under 35 U.S.C. 103 as being unpatentable over Oda et al. (2008/0237467 A1; hereinafter Oda) in view of Meynants (2020/0194474 A1; hereinafter Meynants).
Regarding Claim 1, Oda (fig. 1) teaches an infrared detector ([0051], 1) based on a CMOS process, comprising:
a CMOS measuring circuit system ([0051], 2a) and a CMOS infrared sensing structure (every component above 2a, referred to as CMOS infrared sensing structure, see annotated fig. 1), wherein both the CMOS measuring circuit system (2a) and the CMOS infrared sensing structure are fabricated using the CMOS process ([0058], 2a may be a CMOS), and wherein the CMOS infrared sensing structure (CMOS infrared sensing structure) is directly fabricated on the CMOS measuring circuit system (2a); wherein
the CMOS infrared sensing structure (CMOS infrared sensing structure) includes at least one sealed release isolation layer ([0051], 5) above the CMOS measuring circuit system (2a), wherein the sealed release isolation layer (5) is configured to protect ([0059], 5 protects 3 and 4 below it) the CMOS measuring circuit system (2a) from process influence during an etching course for fabricating the CMOS infrared sensing structure; wherein
the CMOS infrared sensing structure (CMOS infrared sensing structure) comprises at least two metal interconnect layers ([0051], 3, 9), at least two dielectric layers ([0051], 7) and a plurality of interconnect through holes ([0051], holes where contacts 4 are formed),
the dielectric layer (7) comprises at least one sacrificial layer and one thermal-sensitive dielectric layer ([0051], 7), wherein
the metal interconnect layer (3, 9) comprises at least a reflecting layer (3) and an electrode layer (9); wherein
the thermal-sensitive dielectric layer (7) comprises a thermal-sensitive material with a temperature coefficient of resistance greater than a predetermined value ([0062], may be a material with a large temperature coefficient resistance), wherein the thermal-sensitive dielectric layer (7) is configured to convert a temperature change corresponding to infrared radiation absorbed by the thermal-sensitive dielectric layer (7) into a resistance change, and then convert an infrared signal into an electrically readable signal ([0045]) by the CMOS measuring circuit system (2a), wherein the infrared signal corresponds to the resistance change ([0045]); wherein
the CMOS infrared sensing structure (CMOS infrared sensing structure) comprises a resonant cavity ([0052], gap between 3 and 14, labeled as 15, see fig. 1) formed by the reflecting layer (3) and the thermal-sensitive dielectric layer (7),
a suspended micro-bridge structure ([0067], combination of 14, 13, and 9) for controlling heat transfer, and
a columnar structure ([0051], 4) with electrical connection and supporting functions ([0051]), wherein the CMOS measuring circuit system (2a) is configured to measure and process a value of an array resistor ([0051], 14) formed by one or more CMOS infrared sensing structures (1) and convert the infrared signal corresponding to the value of the array resistor (14) into an image electrical signal ([0045]).
Oda doesn’t explicitly teach the CMOS infrared sensing structure fabricated using the CMOS process.
However, Meynants (fig. 7) the CMOS infrared sensing ([0064], image sensor) structure fabricated using the CMOS process ([0051]). Meynants also teaches that this allows for mass-manufacturing with good repeatability.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the infrared detector of Oda to include the CMOS infrared sensing structure of Meynants to allow for repeatable mass-manufacturing.
Additionally, Claim 1 is a product-by-process claim. A product-by-process claim is a product claim. Applicant has merely chosen to define the claimed product by the process by which it was made. It has been well established that process limitations do not impart patentability to an old/obvious product. Process limitations are significant only to the extent that they distinguish the claimed product over the prior art product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985).
In this case, anticipation of Claim 1 does not require “the CMOS infrared sensing structure is directly fabricated on the CMOS measuring circuit system”, but simply that the CMOS infrared sensing structure is directly on the CMOS measuring circuit system. Additionally, it does not require “at least two dielectric layers” and “the dielectric layer comprises at least one sacrificial layer”, because the sacrificial layer is etched away prior to the formation of the finished claimed invention. Additionally, it does not require “the CMOS measuring circuit system and the CMOS infrared sensing structure are fabricated using the CMOS process”, but simply that they are both CMOS. Once the Examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir.1983).
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Annotated Figure 1
Regarding Claim 2, Oda (fig. 1) teaches the infrared detector based on the CMOS process according to claim 1, wherein the CMOS infrared sensing structure (CMOS infrared sensing structure) is fabricated in an upper layer (CMOS infrared sensing structure is formed above 2a) or in the same layer of the metal interconnection layer of the CMOS measuring circuit system (metal components of 2a).
Regarding Claim 3, Oda (fig. 1) teaches the infrared detector based on the CMOS process according to claim 1, wherein the sacrificial layer is configured to enable the CMOS infrared sensing structure (CMOS infrared sensing structure) to form a hollow structure (gap between 3 and 14, labeled as 15), a material of the sacrificial layer is silicon oxide, and wherein the sacrificial layer is etched using a post-CMOS process.
Additionally, Claim 3 is a product-by-process claim. A product-by-process claim is a product claim. Applicant has merely chosen to define the claimed product by the process by which it was made. It has been well established that process limitations do not impart patentability to an old/obvious product. Process limitations are significant only to the extent that they distinguish the claimed product over the prior art product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985).
In this case, anticipation of Claim 3 does not require “the sacrificial layer is configured to enable the CMOS infrared sensing structure to form a hollow structure, a material of the sacrificial layer is silicon oxide, and wherein the sacrificial layer is etched using a post-CMOS process”, but simply that the CMOS infrared sensing structure has a hollow structure. Once the Examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir.1983).
Regarding Claim 4, Oda (fig. 1) teaches the infrared detector based on the CMOS process according to claim 3, wherein the post-CMOS process utilizes at least one of gas phase hydrogen fluoride, carbon tetrafluoride and trifluoromethane to etch the sacrificial layer.
Additionally, Claim 4 is a product-by-process claim. A product-by-process claim is a product claim. Applicant has merely chosen to define the claimed product by the process by which it was made. It has been well established that process limitations do not impart patentability to an old/obvious product. Process limitations are significant only to the extent that they distinguish the claimed product over the prior art product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985).
In this case, anticipation of Claim 4 does not require “the post-CMOS process utilizes at least one of gas phase hydrogen fluoride, carbon tetrafluoride and trifluoromethane to etch the sacrificial layer”, but simply that the CMOS infrared sensing structure has a hollow structure as defined in Claim 3. Once the Examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir.1983).
Regarding Claim 5, Oda (fig. 1) teaches the infrared detector based on the CMOS process according to claim 1, wherein the sealed release isolation layer (5) is positioned at an interface between the CMOS measuring circuit system (2a) and the CMOS infrared sensing structure (CMOS infrared sensing structure) or in the CMOS infrared sensing structure, and wherein the sealed release isolation layer (5) is configured to protect the CMOS measuring circuit system (2a) from corrosion during the etching process for releasing the sacrificial layer; and wherein a CMOS process anti-corrosion material used in the sealed release isolation layer (5) comprises at least one of silicon, germanium, silicon-germanium alloy, amorphous silicon, amorphous germanium, amorphous silicon-germanium, amorphous carbon, silicon carbide, aluminum oxide, silicon nitride ([0059]), or silicon carbonitride.
Regarding Claim 6, Oda (fig. 1) teaches the infrared detector based on the CMOS process according to claim infrared detector based on the CMOS process according to claim 1, wherein the CMOS infrared sensing structure (CMOS infrared sensing structure) comprises an absorption plate (14), a beam structure ([0051], 13), the reflecting layer (3), and the columnar structure (4); wherein the absorption plate (14) is configured to absorb the infrared signal and convert the infrared signal into the electrical signal ([0045]), the absorption plate (14) comprises a metal interconnection layer (9) and at least one thermal-sensitive dielectric layer (7), and a material of the thermal-sensitive dielectric layer comprises at least one of amorphous silicon, amorphous germanium, amorphous germanium-silicon, titanium oxide, vanadium oxide ([0062]), or vanadium titanium oxide; wherein the beam structure (13) and the columnar structure (4) are configured to transmit the electrical signal and configured to support and connect ([0051]) the absorption plate (14), wherein the beam structure (13) comprises a metal interconnection layer (9) and at least one dielectric layer ([0051], 6), and wherein the columnar structure (4) is connected to the CMOS measuring circuit system (2a) using the metal interconnection process and the interconnect via process; and wherein the reflecting layer (3) is configured to reflect the infrared signal and form the resonant cavity (gap between 3 and 14, labeled 15) with the thermal-sensitive dielectric layer (7), and wherein the reflecting layer (3) comprises at least one metal interconnection layer ([0058], 3 is metal).
Regarding Claim 7, Oda (fig. 1) teaches the infrared detector based on the CMOS process according to claim 6, wherein the beam structure (13) is electrically connected to at least two ends of the absorption plate (14), the CMOS infrared sensing structure (CMOS infrared sensing structure) comprises at least two columnar structures (4) and at least two support bases (support base, see annotated fig. 1), and wherein the electrode layer (9) comprises at least two electrode terminals (two sides of 9).
Regarding Claim 8, Oda (fig. 1) teaches the infrared detector based on the CMOS process according to claim 1, wherein the infrared detector is fabricated using 3 nm, 7 nm, 10 nm, 14 nm, 22 nm, 28 nm, 32 nm, 45 nm, 65 nm, 90 nm, 130 nm, 150 nm, 180 nm, 250 nm, or 350 nm CMOS process ([0059], components may range from 100 to 500 nm thick).
Regarding Claim 9, Oda (fig. 1) teaches the infrared detector based on the CMOS process according to claim 1, wherein a metal wiring material of the metal interconnection layer (9, 3) comprises at least one of aluminum, copper, tungsten, titanium, ([0058]) nickel, chromium, platinum, silver, ruthenium, or cobalt.
Conclusion
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/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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