Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 13, 2024 was filed in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, requires the specification to be written in “full, clear, concise, and exact terms.” The specification seems to be a translation into English from a foreign document is replete with terms and phrasings which are not clear, concise and exact. Examiner notes in particular that the Specification references specific features which are later referenced in different ways or otherwise are not clearly marked or present in the figures. The specification should be revised carefully in order to comply with 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112.
Claim Objections
The claim set as presented contains grammatical and typographical errors, syntax issues, inconsistent terminology, and verbose phrasings. The claims objected to below are examples of what were identified in an initial review and may not include all objectionable limitations nor claims. Applicant is required to submit claims, as part of a disclosure, conforming to idiomatic English and United States patent practice (See MPEP 702.1).
Claims 1-14 are objected to, below are a few of the issues noted:
Regarding Claim 1,
In a. “provision of a substrate” should read --providing a substrate—and for clarity the limitation and to avoid antecedent issues --wherein the active areas comprise HS transistor active areas and HV transistor active areas-- should be included
In b1. “a masked first ion implantation” should read --a first masked ion implantation-- and “in the active areas intended for the HV transistors” should read --in the HV transistor active areas--
In b2. “a masked second ion implantation” should read --a second masked ion implantation-- and “in the active areas intended for the HS transistors” should read --in the HS transistor active areas--
In c. “on the substrate surface” should read --on a surface of the substrate-- and “HS and HV transistors” should read --HS transistors and HV transistors--
In d. “a second conductivity type, opposite the first” should read --a second conductivity type, of an opposite charge type of the first conductivity type--, “where during the non-selective” should read --wherein during the non-selective-- and “and where the deposition of the buffer layer, the base layer, and the cap layer takes” should read --and wherein the epitaxial deposition of the buffer layer and non-selective epitaxial deposition of the monocrystalline base layer and monocrystalline cap layer take--
In e. “a window in insulator layers of the insulator layer stack” should read --a window in the insulator layer stack--
In g. “anisotropic back-etching with stopping on the remaining part” should read --anisotropic back-etching through to a remaining part--
In h. “the cap layer” should read --the monocrystalline cap layer--
In i. “epitaxial deposition of a highly doped, monocrystalline or polycrystalline emitter layer of the first conductivity type” should read --epitaxial deposition of a highly doped emitter layer of the first conductivity type, wherein the highly doped emitter layer is monocrystalline or polycrystalline--
In j. “patterning of the insulator layer sequence, the emitter layer and the insulator layer for forming a T-shaped emitter, and production of lateral spacers at the outward-facing side faces of the emitter layer and of the insulator layer” should read --patterning of the insulator layer sequence, the highly doped emitter layer, and an insulator layer for forming a T-shaped emitter, and production of lateral spacers at outward-facing side faces of the highly doped emitter layer and of the insulator layer--
In k. “exposure of the cap layer in regions outside the emitter and selective epitaxy of a height extension of a base terminal layer of the polycrystalline layer stack with in situ doping of the same conduction type as the base; the conductivity of the base terminal may optionally be increased by a following ion implantation” should read --exposure of the monocrystalline cap layer in regions outside the T-shaped emitter and selective epitaxy of a height extension of a base terminal layer of the polycrystalline layer stack with in situ doping of the second conductivity type; subsequently a following ion implantation may be performed to increase a conductivity of the base terminal layer--
In l. “patterning of the parts of the buffer, base, cap and heightened base terminal layers deposited on the base terminal areas, for the removal of said layers from collector terminal areas” should read --patterning of parts of the buffer layer, the monocrystalline base layer, the monocrystalline cap layer, and the base terminal layer within base terminal areas, for the formation of collector terminal areas--
Regarding Claim 2,
“the process as claimed in claim 1, in which” should read --the process of claim 1, wherein-- and “after the formation of the collector areas of the HV or/and HS transistors, in step b, additionally, a silicon buffer layer is selectively epitaxially deposited on the exposed collector areas.” should read --after the formation of the high-conductivity HV collector area and/or high-conductivity HS collector area, a silicon buffer layer is selectively epitaxially deposited on an exposed surface of the high-conductivity HV collector area and/or high-conductivity HS collector area.--
Regarding Claim 3,
“the process as claimed in claim 1, in which” should read --the process of claim 1, wherein-- and “the ion implantations of the collector areas of the HS-HBTs and of the HV-HBTs are implemented such that a border of a collector-substrate space charge zone is embodied less deep in the substrate on the side of said zone lying closer to the substrate surface than a bottom of the field isolation areas” should read --the first masked ion implantation and/or the second masked ion implantation is implemented such that a border of a collector-substrate space charge zone is embodied less deeply into the substrate on a side of the collector-substrate space charge zone lying closer to the surface of the substrate than a bottom of the field isolation areas--
Regarding Claim 4,
“the process as claimed in claim 1, in which” should read --the process of claim 1, wherein-- and “the crystal lattice of the Si substrate, disrupted during the collector implantation, undergoes low-defect reconstruction by means of a heat treatment” should read --the substrate comprises Si and a crystal lattice of the substrate undergoes low-defect reconstruction, by means of a heat treatment, during the first masked ion implantation and/or the second masked ion implantation.--
Regarding Claim 5,
“the process as claimed in claim 1, in which” should read --the process of claim 1, wherein-- and “the production of the isolation areas comprises the deposition initially of a first SiO2 layer” should read --the field isolation areas are formed by an initial deposition of a first SiO2 layer--
Regarding Claim 6,
“the process as claimed in claim 5” should read --the process of claim 5--
Regarding Claim 7,
“the process as claimed in claim 6, in which” should read --the process of claim 6, wherein--, “ablation” should read --removal--, and “in the windows defined by means of a resist mask, by means of one or more dry etching steps, wherein an etching time in the dry etching step” should read --within the collector windows, as defined by a resist mask, through a dry etching process, wherein the dry etching process comprises one or more dry etching steps and an etching time for the one or more dry etching steps--
Regarding Claim 8,
“the process as claimed in claim 1, comprising” should read --the process of claim 1, further comprising-- and “over the cap layer” should read --over the monocrystalline cap layer--
Regarding Claim 9,
“the process as claimed in claim 1, in which” should read --the process of claim 1, wherein-- and “little or no ablation” should read --little or no removal--
Regarding Claim 10,
“the process as claimed in claim 9” should read --the process of claim 9-- and “implementation of the selective ion implantations for the formation of the HS-SIC doping and/or of the HV-SIC doping in a self-aligned way for the emitter window, wherein areas outside the emitter window are protected from the implantation by the insulator layer stack” should read --the HS-SIC doping and/or the HV-SIC doping is implemented in a self-aligned way for the emitter window, wherein areas outside the emitter window are protected from implantation by the insulator layer stack--
Regarding Claim 11,
“the process as claimed in claim 1, in which” should read --the process of claim 1, wherein-- and “by means of a carrier gas which contains bis(tert-butylamino)silane” should read --wherein a carrier gas of the low-pressure CVD procedure comprises bis(tert-butylamino)silane--
Regarding Claim 12,
“the process as claimed in claim 1, in which” should read --the process of claim 1, wherein-- and “configured as a layer sequence of four individual layers of silicon oxide, silicon nitride, silicon oxide and silicon nitride” should read --configured as a four sublayer sequence comprising a first silicon oxide sublayer, a first silicon nitride sublayer, a second silicon oxide sublayer, and a second silicon nitride sublayer--
Regarding Claim 13,
“the process as claimed in claim 1, in which” should read --the process of claim 1, wherein--, “the emitter” should read --the T-shaped emitter--, “the silicon nitride layer i5” should read –the silicon nitride layer-- and “to provide near- surface regions of the base and of the cap layer, outside the internal transistor areas, with a high concentration of defects of the same conductivity type as the base” should read --to provide a high concentration of defects of the second conductivity type to near-surface regions of the monocrystalline base layer and of the monocrystalline cap layer, wherein the near-surface regions are outside the internal transistor areas of the HS transistors and HV transistors--
Regarding Claim 14,
In b1. “in the active areas intended for the HV transistors, respectively a coherent highly conductive HV collector area” should read --wherein the HV transistor active areas comprise a contiguous highly conductive HV collector area--
In b2. “in the active areas intended for the HS transistors, respectively a coherent highly conductive HS collector area” should read --wherein the HS transistor active areas comprise a contiguous highly conductive HS collector area—
In c1. “a first selective collector doping, hereinafter HV-SIC doping, which may also be present in the HS transistor areas” should read --wherein the HS transistor active areas may further comprise a first selective collector doping--
And so forth in the remaining portions of Claim 14. Please refer to corrections made to the method limitations of Claim 1 as can be applied to the device of Claim 14. Specifically, see objections to sections d-l of Claim 1 above to sections c2-g of Claim 14.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims are generally narrative and indefinite, failing to conform with current U.S. practice. They appear to be a literal translation into English from a foreign document and are replete with grammatical and idiomatic errors. This consequently results in numerous terms lacking antecedent basis and a lack of clarity as to the claimed invention established by the limitations. Furthermore, due to the lack of a clear chronology and distinction between steps in the methods claims, there is uncertainty regarding optionality in certain processes, whether certain antecedent issues are technically present, and the intended total methodology.
In the following 112(b) claim rejections, the Examiner is taking corrected limitations as given in the Claim Objections above. In the case where corrections are not applied, additional clarity and/or antecedent basis issues may be present. Applicant is strongly encouraged to carefully review amendments to claim limitations before submission of a response.
Regarding Claim 1,
In b. the limitation “subsequently, optionally” is unclear as to what it is subsequent to while there is no clarity as to what is considered optional following it. In the case wherein the optionality applies purely to b1 and b2, there is inconsistent applicability in latter steps / dependent claims with some giving options based on a selection of just b1 or b2 (e.g. Claim 2) while others refer to the implementation of both b1 and b2 (e.g. Claim 3), in the case that neither is implemented, the majority of the latter steps / dependent claims are inapplicable, and it is unclear if this is intended. For brevity, issues in latter limitations regarding this optionality will not be repeated, but still lead to issues of clarity regarding the intended invention. Thus it is unclear how such steps are optional if latter limitations may require both, this renders the limitation indefinite.
For examination purposes both b1 and b2 will be considered as utilized/performed.
In f. the limitation “same doping type” is unclear as to whether this is in reference to the conductivity type, a material used as a dopant, or the process by which the ion implantation is implemented.
For examination purposes the limitation shall be read as --same conductivity type--
Also in f. The limitation “optionally after the deposition of the buffer layer, if the depositions in step d are performed in two separate epitaxy steps, or after opening of the emitter windows in step e, comprising” is unclear as to whether the optionally is in reference to the applicability of the ion implantations of the same doping type overall, the chronology of the ion implantations of the same doping type (being after the listed steps), or whether the applicability of the ion implantations of the same doping type is optionally dependent on any of the listed steps.
For examination purposes the limitation shall be read as referencing chronological timing, being performed after any of the steps listed.
In f1-f3. The limitations “where provided” are unclear whether they reference the structural locations of the HV transistors and HS transistors, or if they are conditional limitations (e.g. ‘if the HS transistors are provided’…).
For examination purposes the limitation “where provided” is understood as relating to structural position
Furthermore, the limitation “choice of the implantation conditions” in f3 is unclear whether the following limitation is necessary or optional, or is in reference to the consequence of the implantation conditions resulting in the desired structure.
For examination purposes the limitation shall be understood as referencing the consequence of the implantation conditions resulting in the desired structure.
In h. the limitation “formed by the monocrystalline cap layer” is unclear, as step e establishes that the emitter window is defined by opening of a window in the insulator layer stack.
For examination purposes the limitation shall be understood as referencing the structural position.
Regarding Claims 2-4, the claims are rejected to due to their dependence on Claim 1.
Regarding Claim 5, beyond the dependency on Claim 1 and optionality issues discussed above, the limitation “the rates of the layers and is greater”, lacks clarity and antecedent basis.
For examination purposes the “layers” shall be read as “the first SiO2 layer and the second SiO2 layer”
“the layer is generated preferably by means of low-pressure CVD-TEOS and the layer is generated preferably by means of plasma-enhanced oxide deposition”, and “the layer is preferably thicker than the layer” are entirely unclear and appear contradictory.
For examination purposes the limitations shall be read as follows:
--the first SiO2 layer is generated preferably by means of low-pressure CVD-TEOS and the second SiO2 layer is generated preferably by means of plasma-enhanced oxide deposition--
--the second SiO2 layer is preferably thicker than the first SiO2 layer--
Regarding Claims 6-13, the claims are rejected to due to their dependence on Claim 1.
Regarding Claim 14,
In c2. The limitation “an additional second selective collector doping” is unclear as it references the presence of a first selective collector doping, but c1 provides optionality to the first selective collector doping, and it is thus unclear whether this limitation is conditionally dependent on the presence of a first selective collector doping.
For examination purposes both the first and second selective collector doping will be present.
The limitation “where the dopings of the collector areas are selected such that the vertical extent of the base-collector space charge zone is greater in the HV transistor than in the HS transistor” is unclear as to which dopings are being referenced and what is meant by “the vertical extent”. In addition, “the vertical extent” and “the base-collector space charge zone” lack antecedent basis.
For examination purposes “the dopings” will be read as --the first selective collector doping and the second selective collector doping--
In d. the limitation “within the respectively same active area, surrounded by the same field isolation area, in which the respective base layer stack is arranged” is unintelligible and lacking antecedent bases.
For examination purposes the limitation shall be read as --within the HS transistor active area and the HV transistor active area--
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable by Chevailer (U.S. Pub. 2019/0140072), in view of Jain et al. (U.S. Pub. 2017/0365695), hereinafter Jain. Both references are included in the IDS filed June 13, 2024.
Regarding Claim 14, Chevailer teaches a bipolar or BiCMOS semiconductor device comprising high-speed bipolar transistors, hereinafter HS transistors, and high-voltage bipolar transistors, hereinafter HV transistors (‘substrate’ containing HS and HV transistors; Fig. 18A (HV) and 18B (HS), Paragraphs [0007] and [0059]), comprising:
a. a substrate ((101); Figs. 18A/18B, Paragraph [0023]) having active areas (e.g. area in and above (105); Figs. 18A/18B, Paragraph [0023]) and shallow trenchlike field isolation areas ((103); Figs. 18A/18B, Paragraph [0023]) which laterally surround the active areas;
bl. in the active areas intended for the HV transistors, respectively a coherent highly conductive HV collector area of a first conductivity type ((105); Fig. 18A); and
b2. in the active areas intended for the HS transistors, respectively a coherent highly conductive HS collector area of the first conductivity type ((105); Fig. 18B);
cl. a first selective collector doping, hereinafter HV-SIC doping, which may also be present in the HS transistor areas ((125); Figs. 18A/18B, Paragraph [0030]), and
c2. an additional second selective collector doping, hereinafter HS-SIC doping, which is present exclusively in the HS transistors in the respective internal transistor area ((126); Fig. 18A, Paragraph [0031]),
d. within the respectively same active area, surrounded by the same field isolation area, in which the respective base layer stack is arranged, a collector terminal area ((163); Figs. 18A/18B, Paragraph [0045]), which connects the collector area of the HS transistors and of the HV transistors to a collector contact ((165); Figs. 18A/18B, Paragraph [0045]);
e. in a collector window of the HV transistors and of the HS transistors that is bounded by insulator layers ((107), (119), (115)); Figs. 18A/18B, Paragraphs [0024], [0027]), respectively a base layer stack which comprises an epitaxial buffer layer (top layer of (125); Fig. 18A/18B, Paragraph [0020]), a monocrystalline, non-selectively epitaxially deposited base layer of a second conductivity type ((127a); Figs. 18A/18B, Paragraph [0033]), opposite to the first, and a monocrystalline cap layer ((127b); Figs. 18A/18B, Paragraph [0033]), where, owing to the non-selective epitaxial deposition of the base layer on the insulator layers in the region of the base layer and of the cap layer, a layer stack of a base terminal area ((109); Fig. 18A/18B, Paragraph [0024]), said stack following at least these layers in polycrystalline form, is arranged;
f. embedded into base-emitter spacers and into a further insulator layer (115) of the HV transistors and of the HS transistors, respectively a highly doped, monocrystalline or polycrystalline, T-shaped emitter layer ((133); Figs. 18A/18B, Paragraph [0036]) of the first conductivity type and lateral spacers ((141); Figs. 18A/18B, Paragraph [0038] at outward-facing side faces of the emitter layer and of the further insulator layer; and
g. outside the emitter of the HV transistors and of the HS transistors, respectively a height extension of the base terminal layer ((153); Figs. 18A/18B, Paragraph [0042]).
Chevailer fails to teach:
the vertical extent of the base-collector space charge zone is greater in the HV transistor than in the HS transistor;
As best understood by the examiner.
Jain teaches a device including HV and HS transistors ((144) and (142), respectively; Fig. 10, Paragraph [0049]):
-the vertical extent of the base-collector space charge zone is greater in the HV transistor (corresponding to (124); Fig. 10, Paragraph [0044]) than in the HS transistor (corresponding to (112); Fig. 10, Paragraph [0040];
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Jain into the device of Chevailer such that the vertical extent of the basecollector space charge zone is greater in the HV transistor than in the HS transistor. This would be due to the fact that doing so would improve the high voltage characteristics of the HV transistors (Jain, Paragraph [0047]).
Allowable Subject Matter
Claims 1-13 would be allowable if rewritten or amended to overcome the rejections under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter as best understood by the Examiner:
Regarding Claim 1, the best prior art of record does not teach or fairly suggest, along with the other claimed features, which are necessary in establishing the methodology, a process for producing high-speed bipolar transistors, hereinafter HS transistors, or/and high-voltage bipolar transistors, hereinafter HV transistors, as part of the implementation of a bipolar or BiCMOS production procedure, comprising:
- deposition of a silicon dioxide layer and formation of base-emitter spacers within the emitter window by partial anisotropic back-etching of the silicon dioxide layer by means of a dry etching process, and formation of auxiliary spacers in the emitter window by deposition of a silicon nitride layer and subsequent anisotropic back-etching through to a remaining part of the silicon dioxide layer;
Regarding Claims 2-13, the claims are allowable based on their dependence on Claim 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRI MIHALIOV whose telephone number is (571)270-5220. The examiner can normally be reached weekdays 7:30 - 17:30 US Eastern Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DMITRI MIHALIOV/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights