DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims
Applicant’s Claims filed on 06/17/2024 regarding claims 1-14 is fully considered. Of the above claims, claims 1-14 have been amended.
Claim Objections
Claims 1, 13 and 14 is objected to because of the following informalities:
Regarding claim 1, the recitation of “the predicted test time length” in line 10 lacks antecedent basis.
Regarding claim 13, the recitation of “the predicted test time length” in lines 7-8 lacks antecedent basis.
Regarding claim 14, the recitation of “the predicted test time length” in lines 8-9 lacks antecedent basis.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-14 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claim(s) recite(s) the steps of “calculate a test time length…,” “predict a current test time length…,” and “predict… an end time of the test… based on the predicted test time length,” all appearing to be mental processes. This judicial exception is not integrated into a practical application because the claimed memory and processor storing program instructions amount to mere instructions to apply an exception on a generic computer under MPEP 2106.05(f) and storing predictions in a readable manner could also be described that way, or as insignificant extra-solution activity under MPEP 2106.05(g). The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because a memory, processor, and storing data are all well understood, routine and conventional (as evidenced by Kagami WO 2019/064876 A1).
Further regarding claims 7-10, in addition to the explanations to claim 6 above, the additional element of “a plurality of blocks” does not amount to significantly more than the judicial exception because blocks are well understood, routine and conventional (as evidenced by Takada JP 2008-268071 A).
Further regarding claim 11, in addition to the explanations to claim 1 above, the additional step of “delete the acquired start time …” does not amount to significantly more than the judicial exception because deleting from memory is well understood, routine and conventional (as evidenced by Takada JP 2008-268071 A).
Further regarding claim 12, in addition to the explanations to claim 1 above, the additional elements of “a test system” and “a test device” do not amount to significantly more than the judicial exception because a test system and a test device are well understood, routine and conventional (as evidenced by Kagami WO 2019/064876 A1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 5-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kagami (WO 2019/064876 A1) in view of Takada (JP 2008-268071 A).
Regarding claim 1, Kagami teaches a prediction device (when the test is performed by the test execution unit 121 of the tester control unit 60 and the test has progressed to a predetermined stage, the time when the test is completed can be predicted; page 35; Figs 1, 6) comprising:
a processor (in the tester control unit 60, the CPU 211 controls each tester by executing a program stored in the storage medium of the ROM 213 or the storage device 205 using the RAM 212 as a work area; page 35; Figs 1, 5-6); and
a memory storing program instructions (in the tester control unit 60, the CPU 211 controls each tester by executing a program stored in the storage medium of the ROM 213 or the storage device 205 using the RAM 212 as a work area; page 35; Figs 1, 5-6) that cause the processor to:
predict, when a start time of a test of a test target wafer by the tester is acquired, an end time of the test of the test target wafer (the scheduled test end time acquisition unit 122 acquires the scheduled test end time at a predetermined stage at which the scheduled test end time can be predicted; page 35; the inspection contents at this time consist of a plurality of parts, and after the inspection start, initial setting, contact confirmation, and actual inspection are performed; page 36; the wafer W to be inspected is mounted on the tester 50, and the inspection is started in step 30; page 37; the start time being after mounting the wafer W in step 30); and
store at least the predicted end time in a readable manner (the storage devices 105 and 205 is adapted to record and read information on a computer readable storage medium; page 35).
Further regarding claim 1, Kagami does not teach the program instructions that cause the processor to:
calculate a test time length when a test of a wafer has been performed by a tester; and
predict a current test time length based on past test time lengths calculated by the processor,
wherein the predicted end time is based on the predicted test time length.
Further regarding claim 1, Takada teaches program instructions that cause a processor to:
calculate a test time length when a test of a wafer has been performed by a tester (the test time measuring unit 23 measures a test time required for performing a test on each LSI; [0005]); and
predict a current test time length based on past test time lengths calculated by the processor (the test time accumulating unit 27 sequentially accumulates test times required for performing tests on individual LSIs to obtain a sum of test times for all LSIs formed on the wafer 40 currently being tested; [0009]),
wherein the predicted end time is based on the predicted test time length (the end time prediction calculation unit 26 is based on the average test time stored in the average test time storage unit 22 and the remaining number of measurement LSIs to be tested that are counted by the measurement LSI counting unit 25; [0008]) for the purpose of improving the operating rate of an LSI tester and a test system for testing individual LSIs formed on a wafer.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate the program instructions that cause the processor to: calculate a test time length when a test of a wafer has been performed by a tester; and predict a current test time length based on past test time lengths calculated by the processor, wherein the predicted end time is based on the predicted test time length, as taught by Takada, into Kagami for the purpose of improving the operating rate of an LSI tester and a test system for testing individual LSIs formed on a wafer.
Regarding claim 5, Kagami does not teach wherein the program instructions cause the processor to predict the end time of the test of the test target wafer by adding the current test time length to the start time of the test of the test target wafer.
Further regarding claim 5, Takada teaches the program instructions cause the processor to predict the end time of the test of the test target wafer by adding the current test time length to the start time of the test of the test target wafer (the end time prediction calculation unit 26 is based on the average value of normal test times of good LSIs sequentially calculated by the normal test time averaging unit 29 and the remaining number of measurement LSIs to be tested that are counted by the measurement LSI counting unit 25; [0027]; end time is based on average value of normal test times from the start time) for the purpose of improving the operating rate of an LSI tester and a test system for testing individual LSIs formed on a wafer.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the program instructions cause the processor to predict the end time of the test of the test target wafer by adding the current test time length to the start time of the test of the test target wafer, as taught by Takada, into Kagami for the purpose of improving the operating rate of an LSI tester and a test system for testing individual LSIs formed on a wafer.
Regarding claim 6, Kagami does not teach wherein the program instructions cause the processor to predict the end time each time the start time is acquired.
Further regarding claim 6, Takada teaches the program instructions cause the processor to predict the end time each time the start time is acquired (the end time prediction calculation unit 26 is based on the average value of normal test times of good LSIs sequentially calculated by the normal test time averaging unit 29 and the remaining number of measurement LSIs to be tested that are counted by the measurement LSI counting unit 25; [0027]; FIG. 2; end time is predicted at the start of testing of each wafer) for the purpose of improving the operating rate of an LSI tester and a test system for testing individual LSIs formed on a wafer.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the program instructions cause the processor to predict the end time each time the start time is acquired, as taught by Takada, into Kagami for the purpose of improving the operating rate of an LSI tester and a test system for testing individual LSIs formed on a wafer.
Regarding claim 7, Kagami does not teach wherein the test includes a plurality of blocks having test items different from each other,
wherein the program instructions cause the processor to calculate an execution time length of each of the plurality of blocks, and
wherein the program instructions cause the processor to predict the current test time length by predicting a current execution time length of each block based on a past execution time length of each block calculated by the processor and by adding the predicted current execution time length of each block.
Further regarding claim 7, Takada teaches the test includes a plurality of blocks having test items different from each other (testing individual LSIs formed on a wafer; [0001]),
wherein the program instructions cause the processor to calculate an execution time length of each of the plurality of blocks (the test time accumulating unit 27 sequentially accumulates test times required for performing tests on individual LSIs to obtain a sum of test times for all LSIs formed on the wafer 40 currently being tested; [0009]), and
wherein the program instructions cause the processor to predict the current test time length by predicting a current execution time length of each block based on a past execution time length of each block calculated by the processor and by adding the predicted current execution time length of each block (the end time prediction calculation unit 26 is based on the average value of normal test times of good LSIs sequentially calculated by the normal test time averaging unit 29 and the remaining number of measurement LSIs to be tested that are counted by the measurement LSI counting unit 25; [0027]; time lengths for remaining LSIs are predicted) for the purpose of improving the operating rate of an LSI tester and a test system for testing individual LSIs formed on a wafer.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the test includes a plurality of blocks having test items different from each other, wherein the program instructions cause the processor to calculate an execution time length of each of the plurality of blocks, and wherein the program instructions cause the processor to predict the current test time length by predicting a current execution time length of each block based on a past execution time length of each block calculated by the processor and by adding the predicted current execution time length of each block, as taught by Takada, into Kagami for the purpose of improving the operating rate of an LSI tester and a test system for testing individual LSIs formed on a wafer.
Regarding claim 8, Kagami does not teach wherein the program instructions cause the processor to predict, when an execution start time of any one of the plurality of blocks is acquired, the end time of the test of the test target wafer based on an execution time length predicted for each block as of a block for which the execution start time is acquired.
Further regarding claim 8, Takada teaches the program instructions cause the processor to predict, when an execution start time of any one of the plurality of blocks is acquired, the end time of the test of the test target wafer based on an execution time length predicted for each block as of a block for which the execution start time is acquired (the end time prediction calculation unit 26 is based on the average value of normal test times of good LSIs sequentially calculated by the normal test time averaging unit 29 and the remaining number of measurement LSIs to be tested that are counted by the measurement LSI counting unit 25; [0027]; end time is predicted when the execution start time of the first LSI is determined) for the purpose of improving the operating rate of an LSI tester and a test system for testing individual LSIs formed on a wafer.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the program instructions cause the processor to predict, when an execution start time of any one of the plurality of blocks is acquired, the end time of the test of the test target wafer based on an execution time length predicted for each block as of a block for which the execution start time is acquired, as taught by Takada, into Kagami for the purpose of improving the operating rate of an LSI tester and a test system for testing individual LSIs formed on a wafer.
Regarding claim 9, Kagami does not teach wherein the program instructions cause the processor to store the acquired start time and the predicted execution time length of each block in a readable manner.
Further regarding claim 9, Takada teaches the program instructions cause the processor to store the acquired start time and the predicted execution time length of each block in a readable manner (the average test time storage unit 22 stores an average test time required for performing a test on each LSI measured in advance; [0004]) for the purpose of improving the operating rate of an LSI tester and a test system for testing individual LSIs formed on a wafer.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the program instructions cause the processor to store the acquired start time and the predicted execution time length of each block in a readable manner, as taught by Takada, into Kagami for the purpose of improving the operating rate of an LSI tester and a test system for testing individual LSIs formed on a wafer.
Regarding claim 10, Kagami does not teach wherein the predicted test time length and the predicted execution time length of each block are updated each time the test of the test target wafer is completed or each time execution of any one of the plurality of blocks is ended with respect to the test target wafer,
wherein the acquired start time is stored every time the test of the test target wafer is started, and
wherein the predicted end time is updated each time the test of the test target wafer is started or each time execution of any block of the plurality of blocks is started with respect to the test target wafer.
Further regarding claim 10, Takada teaches the predicted test time length and the predicted execution time length of each block are updated each time the test of the test target wafer is completed or each time execution of any one of the plurality of blocks is ended with respect to the test target wafer (the end time prediction calculation unit 26 is based on the average value of normal test times of good LSIs sequentially calculated by the normal test time averaging unit 29 and the remaining number of measurement LSIs to be tested that are counted by the measurement LSI counting unit 25; [0027]; FIG. 2; time length is predicted after completion of testing of each wafer),
wherein the acquired start time is stored every time the test of the test target wafer is started (the average test time storage unit 22 stores an average test time required for performing a test on each LSI measured in advance; [0004]; data is stored for calculations when water testing is started), and
wherein the predicted end time is updated each time the test of the test target wafer is started or each time execution of any block of the plurality of blocks is started with respect to the test target wafer (the end time prediction calculation unit 26 is based on the average value of normal test times of good LSIs sequentially calculated by the normal test time averaging unit 29 and the remaining number of measurement LSIs to be tested that are counted by the measurement LSI counting unit 25; [0027]; FIG. 2; end time is predicted at the start of testing of each wafer) for the purpose of improving the operating rate of an LSI tester and a test system for testing individual LSIs formed on a wafer.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the predicted test time length and the predicted execution time length of each block are updated each time the test of the test target wafer is completed or each time execution of any one of the plurality of blocks is ended with respect to the test target wafer, wherein the acquired start time is stored every time the test of the test target wafer is started, and wherein the predicted end time is updated each time the test of the test target wafer is started or each time execution of any block of the plurality of blocks is started with respect to the test target wafer, as taught by Takada, into Kagami for the purpose of improving the operating rate of an LSI tester and a test system for testing individual LSIs formed on a wafer.
Regarding claim 11, Kagami does not teach wherein the program instructions cause the processor to delete the acquired start time and the predicted end time each time the test of the test target wafer is completed.
Further regarding claim 11, Takada teaches the program instructions cause the processor to delete the acquired start time and the predicted end time each time the test of the test target wafer is completed (the average test time storage unit 22 stores an average test time required for performing a test on each LSI measured in advance; [0004]; data is stored and deleted during calculations when water testing is completed) for the purpose of improving the operating rate of an LSI tester and a test system for testing individual LSIs formed on a wafer.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the program instructions cause the processor to delete the acquired start time and the predicted end time each time the test of the test target wafer is completed, as taught by Takada, into Kagami for the purpose of improving the operating rate of an LSI tester and a test system for testing individual LSIs formed on a wafer.
Regarding claim 12, Kagami teaches a test system comprising the prediction device (Figs 1-6); and a test device including a plurality of said testers and configured to test the wafer (FIGs. 1-6).
Regarding claim 13, Kagami teaches a prediction method (when the test is performed by the test execution unit 121 of the tester control unit 60 and the test has progressed to a predetermined stage, the time when the test is completed can be predicted; page 35; Figs 1, 6-8) comprising:
predicting, when a start time of a test of a test target wafer by the tester is acquired, an end time of the test of the test target wafer (the scheduled test end time acquisition unit 122 acquires the scheduled test end time at a predetermined stage at which the scheduled test end time can be predicted; page 35; the inspection contents at this time consist of a plurality of parts, and after the inspection start, initial setting, contact confirmation, and actual inspection are performed; page 36; the wafer W to be inspected is mounted on the tester 50, and the inspection is started in step 30; page 37; the start time being after mounting the wafer W in step 30); and
storing at least the predicted end time in a readable manner (the storage devices 105 and 205 is adapted to record and read information on a computer readable storage medium; page 35).
Further regarding claim 13, Kagami does not teach calculating a test time length when a test of a wafer has been performed by a tester; and
predicting a current test time length based on past test time lengths calculated in the calculating of the test time length,
wherein the predicted end time is based on the predicted test time length.
Further regarding claim 13, Takada teaches calculating a test time length when a test of a wafer has been performed by a tester (the test time measuring unit 23 measures a test time required for performing a test on each LSI; [0005]); and
predicting a current test time length based on past test time lengths calculated in the calculating of the test time length (the test time accumulating unit 27 sequentially accumulates test times required for performing tests on individual LSIs to obtain a sum of test times for all LSIs formed on the wafer 40 currently being tested; [0009]),
wherein the predicted end time is based on the predicted test time length (the end time prediction calculation unit 26 is based on the average test time stored in the average test time storage unit 22 and the remaining number of measurement LSIs to be tested that are counted by the measurement LSI counting unit 25; [0008]) for the purpose of improving the operating rate of an LSI tester and a test system for testing individual LSIs formed on a wafer.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate calculating a test time length when a test of a wafer has been performed by a tester; and predicting a current test time length based on past test time lengths calculated in the calculating of the test time length, wherein the predicted end time is based on the predicted test time length, as taught by Takada, into Kagami for the purpose of improving the operating rate of an LSI tester and a test system for testing individual LSIs formed on a wafer.
Regarding claim 14, Kagami teaches a non-transitory computer-readable recording medium having stored therein a prediction program (when the test is performed by the test execution unit 121 of the tester control unit 60 and the test has progressed to a predetermined stage, the time when the test is completed can be predicted; page 35; CPU 111, 211; RAM 112, 212; ROM 113, 213; Figs 1-8) for causing a computer to execute:
predicting, when a start time of a test of a test target wafer by the tester is acquired, an end time of the test of the test target wafer (the scheduled test end time acquisition unit 122 acquires the scheduled test end time at a predetermined stage at which the scheduled test end time can be predicted; page 35; the inspection contents at this time consist of a plurality of parts, and after the inspection start, initial setting, contact confirmation, and actual inspection are performed; page 36; the wafer W to be inspected is mounted on the tester 50, and the inspection is started in step 30; page 37; the start time being after mounting the wafer W in step 30); and
storing at least the predicted end time in a readable manner (the storage devices 105 and 205 is adapted to record and read information on a computer readable storage medium; page 35).
Further regarding claim 14, Kagami does not teach calculating a test time length when a test of a wafer has been performed by a tester; and
predicting a current test time length based on past test time lengths calculated in the calculating of the test time length,
wherein the predicted end time is based on the predicted test time length.
Further regarding claim 14, Takada teaches calculating a test time length when a test of a wafer has been performed by a tester (the test time measuring unit 23 measures a test time required for performing a test on each LSI; [0005]); and
predicting a current test time length based on past test time lengths calculated in the calculating of the test time length (the test time accumulating unit 27 sequentially accumulates test times required for performing tests on individual LSIs to obtain a sum of test times for all LSIs formed on the wafer 40 currently being tested; [0009]),
wherein the predicted end time is based on the predicted test time length (the end time prediction calculation unit 26 is based on the average test time stored in the average test time storage unit 22 and the remaining number of measurement LSIs to be tested that are counted by the measurement LSI counting unit 25; [0008]) for the purpose of improving the operating rate of an LSI tester and a test system for testing individual LSIs formed on a wafer.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate calculating a test time length when a test of a wafer has been performed by a tester; and predicting a current test time length based on past test time lengths calculated in the calculating of the test time length, wherein the predicted end time is based on the predicted test time length, as taught by Takada, into Kagami for the purpose of improving the operating rate of an LSI tester and a test system for testing individual LSIs formed on a wafer.
Claim(s) 2-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kagami (WO 2019/064876 A1) as modified by Takada (JP 2008-268071 A) as applied to claim 1 above, and further in view of Yaegashi (JP 2006-120792 A).
Regarding claim 2, Kagami as modified by Takada does not teach wherein the program instructions cause the processor to predict the current test time length by statistically processing test time lengths of a predetermined number of wafers among the past test time lengths calculated by the processor.
Further regarding claim 2, Yaegashi teaches program instructions cause a processor to predict a current test time length by statistically processing test time lengths of a predetermined number of wafers among the past test time lengths calculated by the processor (there is provided a wafer test time abnormality determination method using a wafer test time, wherein the determination reference value is statistically determined based on past test time record data; [0010]; first, the test time determination reference value counting means 2 statistically calculates a determination reference value for each product and measurement condition based on past test time record data in step S1; [0021]; by statistically calculating test time data of past wafers, it is possible to automatically set a large number of wafers and determination reference values for each measurement condition; [0042]) for the purpose of effectively determining an abnormality of a semiconductor device by performing a test time determination using the actual test time of a wafer.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the program instructions cause the processor to predict the current test time length by statistically processing test time lengths of a predetermined number of wafers among the past test time lengths calculated by the processor, as taught by Yaegashi, into Kagami as modified by Takada for the purpose of effectively determining an abnormality of a semiconductor device by performing a test time determination using the actual test time of a wafer.
Regarding claim 3, Kagami as modified by Takada does not teach wherein the program instructions cause the processor to predict the current test time length by statistically processing test time lengths obtained by removing an outlier among the test time lengths of the predetermined number of wafers.
Further regarding claim 3, Yaegashi teaches the program instructions cause the processor to predict the current test time length by statistically processing test time lengths obtained by removing an outlier among the test time lengths of the predetermined number of wafers (it is desirable to exclude and count out abnormal values exceeding ± s[Symbol font/0x73], s is an arbitrary coefficient; [0037]) for the purpose of excluding abnormal values exceeding a certain range.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the program instructions cause the processor to predict the current test time length by statistically processing test time lengths obtained by removing an outlier among the test time lengths of the predetermined number of wafers, as taught by Yaegashi, into Kagami as modified by Takada for the purpose of excluding abnormal values exceeding a certain range.
Regarding claim 4, Kagami as modified by Takada does not teach wherein the program instructions cause the processor to predict the current test time length each time the test time length is calculated.
Further regarding claim 4, Yaegashi teaches the program instructions cause the processor to predict the current test time length each time the test time length is calculated (judgment reference value calculation formula = average yield / average semiconductor device test time + n[Symbol font/0x73]; [0037]) for the purpose of determining abnormality based on the latest calculation.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the program instructions cause the processor to predict the current test time length each time the test time length is calculated, as taught by Yaegashi, into Kagami as modified by Takada for the purpose of determining abnormality based on the latest calculation.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENDRICK X LIU whose telephone number is (571)270-3798. The examiner can normally be reached MWFSa 10am-8pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Douglas X Rodriguez can be reached at (571) 431-0716. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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23 April 2026
/KENDRICK X LIU/Examiner, Art Unit 2853
/DOUGLAS X RODRIGUEZ/Supervisory Patent Examiner, Art Unit 2853
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