Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The abstract filed on 06/17/2024 has reference numerals which should be avoided in order to have a concise narrative.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 4-12, 13, 15-17 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 9, 13, 16 recite the limitation "a connecting electrode including a front surface electrode formed in contact with the insulating film and having a plurality of opening portions that expose the insulating film on the bottom surface," in lines 5-7 (claims 1 and 9), lines 7-9 (claim 13), lines 6-8 (claim 16). There is insufficient antecedent basis for this limitation “the bottom surface” in the claim. It is not clear if it is referring to the bottom surface of the insulating film or the bottom surface of front surface electrode. For examination purposes, this will be interpreted as the bottom surface of the front surface electrode.
Dependent claims 4-8, 10-12, 15, 17 do not rectify the deficiencies and are likewise rejected.
Claim 11 recites the limitation "… the plurality of notch-shaped opening portions" in line 2. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, this limitation will be interpreted as the plurality of opening portions.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ohuchi et al. (US 20020167085 A1; hereinafter “Ohuchi”) in view of Bibl et al. (US 12009347 B1; hereinafter “Bibl”).
In re claim 9, Ohuchi discloses, in figs. 3A-3D, a semiconductor device comprising:
a semiconductor substrate (a substrate on which the semiconductor device is mounted; ¶47. Hereinafter “Subx”);
a first semiconductor chip 201 (¶40-41) formed on the semiconductor substrate (Subx);
an insulating film 205 formed on the first semiconductor chip 201 (¶41);
a connecting electrode including a front surface electrode (202, 203) (¶40) formed in contact with the insulating film 205 and having a plurality of opening portions (the opening portions in between the patterned rewiring 203) that expose the insulating film 205 on the bottom surface, and
a plating film (204, 211, 207C) (¶40, 41, 44) formed in contact with the front surface electrode (202, 203) and having recessed portions (204, 211) on the side of the front surface electrode (202, 203), the recessed portions being opposed to the opening portions (i.e., the opening portions in between the patterned rewiring 203).
Ohuchi does not expressly disclose the semiconductor chip 201 has a semiconductor layer.
In the same field of endeavor, Bibl discloses, in fig. 22, a semiconductor chip including a semiconductor layer onto which the electrodes 186, 188 are formed (C. 7, paras. 3-4).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains in order to form the semiconductor chip of Ohuchi from semiconductor layers as taught by Bibl in order to control conductivity of the materials inside the chip and make highly reliable chips.
In re claim 11, Ohuchi as modified by Bibl discloses the semiconductor device according to claim 9 outlined above.
Ohuchi further discloses, in figs. 3A-3D, the semiconductor device according to claim 9, wherein the plurality of notch-shaped opening portions (the opening portions in between the patterned rewiring 203) are arranged at regular intervals.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ohuchi in view of Bibl and further in view of Lee et al. (US 20220354062 A1; hereinafter “Lee”).
In re claim 12, Ohuchi as modified by Bibl discloses the semiconductor device according to claim 9 outlined above, but does not expressly disclose wherein a light emitting part is provided on the semiconductor substrate and has a ridge structure including a first-conductivity-type second semiconductor layer, a semiconductor quantum well layer, and a second-conductivity-type third semiconductor layer, and the second-conductivity-type third semiconductor layer and the connecting electrode are electrically connected to each other.
In the same field of endeavor, Lee further discloses, in figs. 6-7, wherein a light emitting part S is provided on the semiconductor substrate 132 (¶62-63) and has a ridge structure S including a first-conductivity-type second semiconductor layer 134, a semiconductor quantum well layer 135, and a second-conductivity-type third semiconductor layer 136 (¶65-67), and the second-conductivity-type third semiconductor layer 136 and the connecting electrode E1 are electrically connected to each other.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Lee into the chip of Ohuchi/Bibl to provide a light emitting device emitting light having a spectrum beneficial to plant growth (¶2-6 of Lee).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ohuchi et al. (US 20020167085 A1; hereinafter “Ohuchi”) in view of Lee et al. (US 20220354062 A1; hereinafter “Lee”).
In re claim 16, Yang discloses, in figs. 3A-3D, a method for manufacturing a semiconductor device comprising:
an insulating film forming step of depositing an insulating film 205 on a first semiconductor chip 201 (¶41);
a front surface electrode forming step of forming a front surface electrode (202, 203) (¶40), on the insulating film 205, having a plurality of opening portions (the opening portions in between the patterned rewiring 203) that expose the insulating film 205 on the bottom surface; and
a plating film forming step of forming a plating film (204, 211, 207C) (¶40, 41, 44) on the front surface electrode (202, 203),
the plating film having recessed portions (204, 211) opposed to the opening portions (i.e., the opening portions in between the patterned rewiring 203) on the side in contact with the front surface electrode (202, 203).
Ohuchi does not expressly disclose a crystal growth step of growing a first semiconductor layer on a semiconductor substrate.
In the same field of endeavor, Lee discloses, in figs. 6-7, a crystal growth step of growing a first semiconductor layer 134 on a semiconductor substrate 131 (¶62-63).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains in order to form the semiconductor chip of Ohuchi from semiconductor layers from a crystal growth step as taught by Lee in order to improve quality of the grown semiconductor films (¶62-63 of Lee).
The combined teachings of Ohuchi and Lee disclose an insulating film forming step of depositing an insulating film (Ohuchi: 205) on the first semiconductor layer (Ohuchi’s layer 201 modified by Lee’s teachings of grown semiconductor layer 134).
Allowable Subject Matter
Claims 1, 4-8, 10, 13, 15, 17 are allowed, provided the 112(b) rejections were overcome.
Prior art of record, Ohuchi et al. (US 20020167085 A1), Bibl et al. (US 12009347 B1), Yang et al. (US 20080061436 A1) have been found to be the closest prior art for claims 1 and 13.
Regarding claim 1, closest prior art of record, discloses a semiconductor device comprising: a semiconductor substrate; a first semiconductor layer formed on the semiconductor substrate; an insulating film formed on the first semiconductor layer; and a connecting electrode including a front surface electrode formed in contact with the insulating film and having a plurality of opening portions that expose the insulating film on the bottom surface, and a plating film formed in contact with the front surface electrode and covering the opening portions, as explained above in claim 1.
However, none of the prior art of record, alone or in combination, expressly discloses the plating film having one portion that extends along one side surface of each opening portion toward the bottom side of the opening portion and has a tip that contacts the insulating film on the bottom surface of the opening portion, the plating film having the other portion that extends along the other side surface opposite the one side surface of the opening portion and has a tip that contacts the insulating film on the bottom surface of the opening portion, the insulating film being exposed on the bottom surface in a void formed in the opening portion by a mutual contact between the one portion and the other portion in the opening portion width direction.
Regarding claim 13, closest prior art of record, discloses a method for manufacturing a semiconductor device, comprising: a crystal growth step of growing a first semiconductor layer on a semiconductor substrate; an insulating film forming step of forming an insulating film on the first semiconductor layer; a front surface electrode forming step of forming a front surface electrode, on the insulating film, having a plurality of opening portions that expose the insulating film on the bottom surface; and a plating film forming step of depositing a plating film so as to cover the opening portions on the front surface electrode, as explained above in claim 16.
However, none of the prior art of record, alone or in combination, expressly discloses the plating film having one portion that extends along one side surface of each opening portion toward the bottom side of the opening portion and has a tip that contacts the insulating film on the bottom surface of the opening portion, the plating film having the other portion that extends along the other side surface opposite the one side surface of the opening portion and has a tip that contacts the insulating film on the bottom surface of the opening portion, the insulating film being exposed on the bottom surface in a void formed in the opening portion by a mutual contact between the one portion and the other portion in the opening portion width direction.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bower et al. (US 20180226287 A1; hereinafter “Bower”) discloses, in fig. 6C, a semiconductor device comprising:
a semiconductor substrate 10 (“A plurality of completed semiconductor devices 22 can be disposed on the support substrate 10 (as shown in FIG. 1B, for example)”; ¶82-85);
a first semiconductor layer 20 formed on the semiconductor substrate 10 (¶82-84);
an insulating film 24 formed on the first semiconductor layer 20 (¶85);
a connecting electrode 25, 27 (¶107) including a front surface electrode 25 formed in contact with the insulating film 24 and having a plurality of opening portions that expose the insulating film 24 on the bottom surface (as best understood; the opening portions between patterned electrical contacts 25 expose the insulating film 24), and
a plating film 27 formed in contact with the front surface electrode 25.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NILUFA RAHIM/Primary Examiner, Art Unit 2893
Prosecution Insights