2022Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election with traverse of Group II: Specie A [FIG. 1a-1b], claims 1-5, 8, 9 and 14 in the reply filed on 08/12/2026 is acknowledged. The traversal is on the ground(s) that “The Requirement Applies the Wrong Legal Standard
The present application is a national stage application under 35 U.S.C. 371 of International Application No. PCT/EP2022/087644 Restriction in a national stage application is governed exclusively by the unity of invention standard of PCT Rule 13, as implemented by 37 C.F.R. 1.475 and 1.499. See MPEP 1893.03(d) and 823. The Requirement, however, is expressly premised on 35 U.S.C. 121 and on the existence of a "serious search and/or examination burden." Neither § 121 restriction practice nor the search-burden standard of MPEP 803 and 808 applies to a § 371 national stage application. The Requirement is therefore improper on its face and should be withdrawn.
Unity of Invention Exists Among All Claims
All pending claims 1-16 share the same special technical feature within the meaning of PCT Rule 13.2 and 37 C.F.R. 1.475(a): the assembly architecture recited in claim 1, namely a first planar stack comprising a selective first active layer (11) and first and second electrically insulated upper electrodes (121, 122), together with second and third stacks extending obliquely or perpendicularly to the plane of the first stack, each comprising a non-volatile resistive memory layer (21, 31) in electrical contact with a side surface of a respective upper electrode. Every claim of Groups I and II, and every claim identified with Species A-D, requires this common technical feature.
With respect to the Group I/Group II restriction, 37 C.F.R. 1.475(b)(1) expressly provides that unity of invention exists between a product and a process specially adapted for the manufacture of that product. Claims 15-16 recite a method for manufacturing the very assembly of claim 1 and are specially adapted for its manufacture. The product/process grouping is therefore a combination expressly permitted in a single national stage application, and the restriction between Groups I and II is contrary to Rule 13.2 and § 1.475(b).
No Prior Art Has Been Cited to Establish Lack of Unity a Posteriori
A technical feature that is shared by all claims can support a lack of unity holding only where the Office demonstrates, by reference to the prior art, that the shared feature does not make a contribution over the prior art, i.e., lack of unity a posteriori. See PCT Rule 13.2; 37 C.F.R. 1.475(a); MPEP 1850. The Requirement cites no prior art whatsoever. Absent any showing that the common special technical feature identified above is not special, the Requirement cannot be sustained under the governing unity standard.”, pages 1-3.
This is not found persuasive because only the “WIPO Publication – Non-English version” submitted, therefore, the Examiner had no way to verify of the same document, thus, entering the US national stage is invalid.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 8-9 and 14 is/are rejected under 35 U.S.C. 102(a)(1)/(2) as being anticipated by HONG (Pub. No.: US 2014/0264244).
Re claim 1, HONG, Fig. 4a teaches an assembly comprising at least two non-volatile resistive memories electrically disposed in parallel with each other and each being electrically connected in series to a selective layer respectively forming at least two selectors, each dedicated to one of the memories, the assembly including:
- a first planar stack, comprising:
-a first active layer (left/right 352, ¶ [0055]) which extends in parallel to a given horizontal plane, the first active layer being said selective layer; and
-a first upper electrode (left 356, [0057]) and a second upper electrode (right 356) which both extend on the first active layer (left/right 352) and which are electrically insulated from each other (by 310, Fig. 3a), the first upper electrode (left 356) being laterally delimited by a side surface, the second upper electrode (right 356) being laterally delimited by another side surface, an insulating layer (310) extending between a part of the side surface of the first upper electrode (left 356) and a part of the side surface of the second upper electrode (right 356) to electrically insulate the first upper electrode from the second upper electrode;
- a second stack, which extends obliquely or perpendicularly to said plane, comprising a second active layer (left 338, [0059]-[0060]), at least a part of the second active layer extending opposite another part of the side surface of the first upper electrode (left 356), the second active layer being in electrical contact with the first upper electrode (left 356), the second active layer being a non-volatile resistive memory layer [0059];
- a third stack, which extends obliquely or perpendicularly to said plane, comprising a third active layer (right 338), at least a part of the third active layer extending opposite another part of the second upper electrode (right 356), the third active layer (right 338) being in electrical contact with the second upper electrode (right 356), the third active layer being a non-volatile resistive memory layer [0060];
- the second (left 338) and third (right 338) active layers being disjoint (by 310), with no direct electrical contact therebetween.
Re claim 2, HONG, Fig. 4a teaches the assembly (1) according to the preceding claim 1,
- comprising a lower electrode (395L, [0065]), which extends beneath the first active layer (left/right 352), in parallel thereto, and which is in electrical contact with a lower face of the first active layer, wherein
- at least a part of the first upper electrode (left 356) is located in vertical alignment (vertically) with the lower electrode (395L), superimposed on the lower electrode, in a projection along a direction perpendicular to said plane, and wherein
- at least a part of the second upper electrode (right 356) is located in vertical alignment with the lower electrode (395L), superimposed on the lower electrode, in a projection along a direction perpendicular to said plane.
Re claim 3, HONG, Fig. 4a teaches the assembly (1) according to the preceding claim 2, wherein at least one of the upper electrodes (right/left 356) is only partially superimposed on the lower electrode (395L).
Re claim 4, HONG, Fig. 4a teaches the assembly according to claim 2, wherein:
- the first and second upper electrodes (left/right 356) are separated from each other, along a given horizontal direction, by a given spacing, and wherein
- along said direction, the first upper electrode (left 356) is superimposed on the lower electrode (395L) over a distance which is less than said spacing.
Re claim 5, HONG, Fig. 4a teaches the assembly according to one of claim 2, wherein the first active layer (left 352) laterally extends beyond the lower electrode (395L), protruding on a dielectric layer (390L) which surrounds the lower electrode (395L, [0078]).
Re claim 8, HONG, Fig. 4a teaches the assembly according to one of the preceding claims, wherein the first and second upper electrodes (left/right 356) are in direct contact with the first active layer (left/right 352).
Re claim 9, HONG, Fig. 4a teaches the assembly according to one of the preceding claims, wherein the first planar stack comprises an insulating layer (395U) which extends above the first and second upper electrodes (left/right 356).
Re claim 14, HONG, Fig. 4a teaches a resistive memory array comprising a plurality of assemblies according to one of the preceding claims, wherein, for each assembly:
- the first planar stack of the assembly is electrically connected to an addressing row (WLn-1, Fig. 2d) of the array,
- the second and third vertical stacks of the assembly (1) are electrically connected to two addressing columns (Bli-2 to BLi) of the array respectively, the two addressing columns being distinct.
Claim(s) 1-2 and 13 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by WAN (Pub. No.: US 2022/0223649).
Re claim 1, WAN, FIGS. 14B-C teaches an assembly comprising at least two non-volatile resistive memories electrically disposed in parallel with each other and each being electrically connected in series to a selective layer respectively forming at least two selectors, each dedicated to one of the memories, the assembly including:
- a first planar stack, comprising:
-a first active layer ([right/middle 152] for claim 2 and [right/middle 152]/151-30 for claim 12, ¶ [0146]) which extends in parallel to a given horizontal plane, the first active layer being said selective layer; and
-a first upper electrode (right 153) and a second upper electrode (middle 153) which both extend on the first active layer ([right/middle 152]/30) and which are electrically insulated from each other (by 156, FIG. 8B, [0149]), the first upper electrode (right 153) being laterally delimited by a side surface, the second upper electrode (middle 153) being laterally delimited by another side surface, an insulating layer (62) extending between a part of the side surface (156) of the first upper electrode (right 153) and a part of the side surface of the second upper electrode (middle 153) to electrically insulate the first upper electrode (right 153) from the second upper electrode (middle 153);
- a second stack, which extends obliquely or perpendicularly to said plane, comprising a second active layer (right [80+40+160+112+114+130]), at least a part of the second active layer extending opposite another part of the side surface of the first upper electrode (right 153), the second active layer (right [80+40+160+112+114+130]) being in electrical contact with the first upper electrode (right 153), the second active layer being a non-volatile resistive memory layer (elements of 130, [0168]));
- a third stack, which extends obliquely or perpendicularly to said plane (P), comprising a third active layer (31), at least a part of the third active layer (middle [80+40+160+112+114+130]) extending opposite another part of the side surface of the second upper electrode (middle 153), the third active layer (middle [80+40+160+112+114+130]) being in electrical contact with the second upper electrode (middle 153), the third active layer being a non-volatile resistive memory layer (material of 130);
- the second and third active layers being disjoint (by 80), with no direct electrical contact therebetween.
Re claim 2, WAN, FIGS. 14B-C teaches the assembly (1) according to the preceding claim 1,
- comprising a lower electrode (151), which extends beneath the first active layer (152), in parallel thereto, and which is in electrical contact with a lower face of the first active layer (bottom surface of 152), wherein
- at least a part of the first upper electrode (right 153) is located in vertical alignment with the lower electrode (right 152), superimposed on the lower electrode, in a projection along a direction perpendicular to said plane, and wherein
- at least a part of the second upper electrode (right 153) is located in vertical alignment with the lower electrode (right 151), superimposed on the lower electrode, in a projection along a direction perpendicular to said plane.
Re claim 12, WAN, FIGS. 14B-C teaches the assembly according to one of claim 1, wherein the first active layer ([right/middle 152/151]/30), common to the second and third stacks (right/middle [112+40+160+112+114+130]), is continuous, in one piece.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over NAVARRO (Pub. No.: US 2019/0198570) in view of HONG.
Re claim 1, WAN, FIGS. 13-14 teaches an assembly comprising at least two non-volatile resistive memories electrically disposed in parallel with each other and each being electrically connected in series to a selective layer respectively forming at least two selectors, each dedicated to one of the memories, the assembly including:
- a first planar stack, comprising:
-a first active layer (503/606, ¶ [0114]/[0143]) which extends in parallel to a given horizontal plane, the first active layer being said selective layer; and
-a first upper electrode (504/right 607) and a second upper electrode (middle 607) which both extend on the first active layer (503/606) and which are electrically insulated from each other (by 609, Fig. 9, [0148]), the first upper electrode (right 607) being laterally delimited by a side surface (side interface between [right 607] and 606), the second upper electrode (middle 607) being laterally delimited by another side surface (side interface between [middle 607] and 606), an insulating layer (609) extending between a part of the side surface of the first upper electrode (right 607) and a part of the side surface of the second upper electrode (middle 607) to electrically insulate the first upper electrode (right 607) from the second upper electrode (middle 607);
- a second stack, which extends obliquely or perpendicularly to said plane, comprising a second active layer (right [508], Fig. 3), at least a part of the second active layer extending opposite another part of the side surface of the first upper electrode (504/right 607), the second active layer (right [508]) being in electrical contact with the first upper electrode (right 504), the second active layer being a non-volatile resistive memory layer [0134];
- a third stack, which extends obliquely or perpendicularly to said plane, comprising a third active layer (middle [508]), at least a part of the third active layer extending opposite another part of the second upper electrode (middle 607), the third active layer (middle [508]) being in electrical contact with the second upper electrode (middle 607), the third active layer being a non-volatile resistive memory layer (middle 508);
- the second (right 508) and third (middle 508) active layers being disjoint (by 608), with no direct electrical contact therebetween.
NAVARRO fails to teach at least a part of the second/third active layer extending opposite another part of the side surface of the first/second upper electrode
HONG teaches at least a part of the second/third active layer (left/right 338) extending opposite another part of the side surface of the first/second upper electrode (left/right 356).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of reducing current as taught by HONG, Abstract.
Conclusion
The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure:
Loy (Pub. No.: US 2021/0020834).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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/TONY TRAN/Primary Examiner, Art Unit 2893
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