DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-16 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-16 of copending Application No. 18/721,012 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because application claims 1-16 are anticipated by claims 1-16 of the copending Application, and it is not patentably distinct from claims 1-16 of the copending Application.
Application Under Examination Claims
copending Application Claims
1. An assembly including at least two selectors electrically disposed in parallel with each other and each being electrically connected in series to a memory layer forming at least two distinct non-volatile resistive memories each associated, respectively, with one of the two selectors, the assembly including:
a first planar stack, comprising:
a first active layer which extends in parallel to a given horizontal plane, the first active layer being said memory layer; and
a first upper electrode and a second upper electrode which both extend on the first active layer and which are electrically insulated from each other, the first upper electrode being laterally delimited by a side surface, the second upper electrode being laterally delimited by another side surface, an insulating layer extending between a part of the side surface of the first upper electrode and a part of the side surface of the second upper electrode to electrically insulate the first upper electrode from the second upper electrode;
a second stack, which extends obliquely or perpendicularly to said plane, comprising a second active layer, at least a part of the second active layer extending opposite another part of the side surface of the first upper electrode, the second active layer being in electrical contact with the first upper electrode, the second active layer being a selective layer;
a third stack, which extends obliquely or perpendicularly to said plane, comprising a third active layer, at least a part of the third active layer extending opposite another part of the side surface of the second upper electrode, the third active layer being in electrical contact with the second upper electrode, the third active layer being another selective layer;
the second and third active layers being disjoint, with no direct electrical contact therebetween.
Anticipated by copending Application Claim 1:
1. An assembly comprising at least two non-volatile resistive memories electrically disposed in parallel with each other and each being electrically connected in series to a selective layer respectively forming at least two selectors, each dedicated to one of the memories, the assembly including:
a first planar stack, comprising:
a first active layer which extends in parallel to a given horizontal plane, the first active layer being said selective layer; and
a first upper electrode and a second upper electrode which both extend on the first active layer and which are electrically insulated from each other, the first upper electrode being laterally delimited by a side surface, the second upper electrode being laterally delimited by another side surface, an insulating layer extending between a part of the side surface of the first upper electrode and a part of the side surface of the second upper electrode to electrically insulate the first upper electrode from the second upper electrode;
a second stack, which extends obliquely or perpendicularly to said plane, comprising a second active layer, at least a part of the second active layer extending opposite another part of the side surface of the first upper electrode, the second active layer being in electrical contact with the first upper electrode, the second active layer being a non-volatile resistive memory layer;
a third stack, which extends obliquely or perpendicularly to said plane, comprising a third active layer, at least a part of the third active layer extending opposite another part of the side surface of the second upper electrode, the third active layer being in electrical contact with the second upper electrode, the third active layer being a non-volatile resistive memory layer;
the second and third active layers being disjoint, with no direct electrical contact therebetween.
2. The assembly according to claim 1,
comprising a lower electrode, which extends beneath the first active layer, in parallel thereto, and which is in electrical contact with a lower face of the first active layer, wherein
at least a part of the first upper electrode is located in vertical alignment with the lower electrode, superimposed on the lower electrode, in a projection along a direction perpendicular to said plane, and wherein
at least a part of the second upper electrode is located in vertical alignment with the lower electrode, superimposed on the lower electrode, in a projection along a direction perpendicular to said plane.
Anticipated by copending Application Claim 2:
2. The assembly according to claim 1,
comprising a lower electrode, which extends beneath the first active layer, in parallel thereto, and which is in electrical contact with a lower face of the first active layer, wherein
at least a part of the first upper electrode is located in vertical alignment with the lower electrode, superimposed on the lower electrode, in a projection along a direction perpendicular to said plane, and wherein
at least a part of the second upper electrode is located in vertical alignment with the lower electrode, superimposed on the lower electrode, in a projection along a direction perpendicular to said plane.
3. The assembly according to claim 2, wherein at least one of the upper electrodes is only partially superimposed on the lower electrode.
Anticipated by copending Application Claim 3:
3. The assembly according to claim 2, wherein at least one of the upper electrodes is only partially superimposed on the lower electrode.
4. The assembly according to claim 2, wherein:
the first and second upper electrodes are separated from each other, along a given horizontal direction, by a given spacing, and wherein
along said direction, the first upper electrode is superimposed on the lower electrode over a distance which is less than said spacing.
Anticipated by copending Application Claim 4:
4. The assembly according to claim 2, wherein:
the first and second upper electrodes are separated from each other, along a given horizontal direction, by a given spacing, and wherein
along said direction, the first upper electrode is superimposed on the lower electrode over a distance which is less than said spacing.
5. The assembly according to claim 2, wherein the first active layer laterally extends beyond the lower electrode, protruding on a dielectric layer.
Anticipated by copending Application Claim 5:
5. The assembly according to claim 2, wherein the first active layer laterally extends beyond the lower electrode, protruding on a dielectric layer which surrounds the lower electrode.
6. The assembly according to claim 1, wherein:
the first active layer is laterally delimited by a side surface, and
the assembly further comprises an electrically insulating spacer which extends at least against the side surface of the first active layer, at least partly covering this the side surface.
Anticipated by copending Application Claim 6:
6. The assembly according to claim 1, wherein:
the first active layer is laterally delimited by a side surface, and
the assembly further comprises an electrically insulating spacer which extends at least against the side surface of the first active layer, at least partly covering this side surface.
7. The assembly according to claim 6, wherein the spacer also covers, only partly, the side surface of at least one of the first and second upper electrodes.
Anticipated by copending Application Claim 7:
7. The assembly according to claim 6, wherein the spacer also covers, only partly, the side surface of at least one of the first and second upper electrodes.
8. The assembly according to claim 1, wherein the first and second upper electrodes are in direct contact with the first active layer.
Anticipated by copending Application Claim 8:
8. The assembly according to claim 1, wherein the first and second upper electrodes are in direct contact with the first active layer.
9. The assembly according to claim 1, wherein the first planar stack comprises an insulating layer which extends above the first and second upper electrodes.
Anticipated by copending Application Claim 9:
9. The assembly according to claim 1, wherein the first planar stack comprises an insulating layer which extends above the first and second upper electrodes.
10. The assembly according to claim 9, comprising a fourth, planar, stack disposed on the insulating layer, the fourth stack comprising:
a fourth active layer which extends in parallel to said plane, the fourth active layer being a memory layer;
a third and a fourth electrode which extend in parallel to said plane, between the fourth active layer and the insulating layer, and which are electrically insulated from each other, the third electrode being laterally delimited by a side surface being laterally delimited by another side surface, an insulating layer extending between a part of the side surface of the third electrode and a part of the side surface of the fourth electrode to electrically insulate the third electrode from the fourth electrode;
wherein the second active layer extends beyond the side surface of the first upper electrode, extending along a part of the side surface of the third electrode,
and wherein the third active layer extends beyond the side surface of the second upper electrode by extending along a part of the side surface of the fourth electrode.
Anticipated by copending Application Claim 10:
10. The assembly according to claim 9, comprising a fourth, planar, stack disposed on the insulating layer, the fourth stack comprising:
a fourth active layer which extends in parallel to said plane, the fourth active layer being a selective layer;
a third and a fourth electrode which extend in parallel to said plane, between the fourth active layer and the insulating layer, and which are electrically insulated from each other, the third electrode being laterally delimited by a side surface, the fourth electrode being laterally delimited by another side surface, an insulating layer extending between a part of the side surface of the third electrode and a part of the side surface of the fourth electrode to electrically insulate the third electrode from the fourth electrode;
wherein the second active layer extends beyond the side surface of the first upper electrode, extending along a part of the side surface of the third electrode,
and wherein the third active layer extends beyond the side surface of the second upper electrode by extending along a part of the side surface of the fourth electrode.
11. The assembly according to claim 10, wherein the fourth stack comprises:
a fifth electrode, which extends above the fourth active layer, in electrical contact with the fourth active layer, and
an electrically insulating third spacer which covers a side surface of the fifth electrode.
Anticipated by copending Application Claim 11:
11. The assembly according to claim 10, wherein the fourth stack comprises:
a fifth electrode, which extends above the fourth active layer, in electrical contact with the fourth active layer, and
an electrically insulating third spacer which covers a side surface of the fifth electrode.
12. The assembly according to claim 1, wherein the first active layer, common to the second and third stacks, is continuous, in one piece.
Anticipated by copending Application Claim 12:
12. The assembly according to claim 1, wherein the first active layer, common to the second and third stacks, is continuous, in one piece.
13. The assembly according to claim 1, wherein the first active layer is divided into a first part and a second part, which are disjoint, the first part of the active layer extending beneath the first upper electrode, the second part of the active layer extending beneath the second upper electrode.
Anticipated by copending Application Claim 13:
13. The assembly according to claim 1, wherein the first active layer is divided into a first part and a second part, which are disjoint, the first part of the active layer extending beneath the first upper electrode, the second part of the active layer extending beneath the second upper electrode.
14. A resistive memory array comprising a plurality of assemblies according to claim 1, wherein, for each assembly:
the first planar stack of the assembly is electrically connected to an addressing row of the array,
the second and third vertical stacks of the assembly are electrically connected to two addressing columns of the array respectively, the two addressing columns being distinct.
Anticipated by copending Application Claim 14:
14. A resistive memory array comprising a plurality of assemblies according to claim 1, wherein, for each assembly:
the first planar stack of the assembly is electrically connected to an addressing row of the array,
the second and third vertical stacks of the assembly are electrically connected to two addressing columns of the array respectively, the two addressing columns being distinct.
15. A method for manufacturing an assembly comprising at least two selectors electrically disposed in parallel with each other and each electrically connected in series to a memory layer forming at least two distinct non-volatile resistive memories each associated, respectively, with one of the two selectors, the method comprising:
forming a first planar stack comprising:
depositing a first active layer-extending in parallel to a given horizontal plane, the first active layer being said memory layer; and
depositing a first upper electrode and a second upper electrode which both extend on the first active layer and which are electrically insulated from each other, the first upper electrode being laterally delimited by a side surface, the second upper electrode being laterally delimited by another side surface, an insulating layer extending between a part of the side surface of the first upper electrode and a part of the side surface of the second upper electrode to electrically insulate the first upper electrode from the second upper electrode;
forming a second stack, which extends obliquely or perpendicularly to said plane, comprising a second active layer, at least a part of the second active layer extending opposite another part of the side surface of the first upper electrode, the second active layer being in electrical contact with the first upper electrode, the second active layer being a selective layer;
forming a third stack, which extends obliquely or perpendicularly to said plane, comprising a third active layer, at least a part of the third active layer extending opposite another part of the side surface of the second upper electrode, the third active layer being in electrical contact with the second upper electrode, the third active layer being another selective layer.
Anticipated by copending Application Claim 15:
15. A method for manufacturing an assembly comprising at least two non-volatile resistive memories electrically disposed in parallel with each other and each electrically connected in series to a selective layer forming at least two selectors respectively, each dedicated to one of the memories, the method comprising:
forming a first planar stack comprising:
depositing a first active layer extending in parallel to a given horizontal plane, the first active layer being said selective layer; and
depositing a first upper electrode and a second upper electrode which both extend on the first active layer and which are electrically insulated from each other, the first upper electrode being laterally delimited by a side surface, the second upper electrode being laterally delimited by another side surface, an insulating layer extending between a part of the side surface of the first upper electrode and a part of the side surface of the second upper electrode to electrically insulate the first upper electrode from the second upper electrode;
forming a second stack, which extends obliquely or perpendicularly to said plane, comprising a second active layer, at least a part of the second active layer extending opposite another part of the side surface of the first upper electrode, the second active layer being in electrical contact with the first upper electrode, the second active layer being a non-volatile resistive memory layer;
forming a third stack, which extends obliquely or perpendicularly to said plane, comprising a third active layer, at least a part of the third active layer extending opposite another part of the side surface of the second upper electrode, the third active layer being in electrical contact with the second upper electrode, the third active layer being another non-volatile resistive memory layer.
16. The method according to claim 15, wherein forming the second and third stacks are performed by carrying out:
conformally depositing an overall active layer, a first part of the overall active layer extending opposite the side surface of the first upper electrode, the first part of the overall active layer being in electrical contact with the first upper electrode, a second part of the overall active layer extending opposite the side surface of the second upper electrode, the second part of the overall active layer being in electrical contact with the second upper electrode;
separating the overall active layer into at least said second active layer and said one third active layer, which are disjoint.
Anticipated by copending Application Claim 16:
16. The method according to claim 15, wherein of forming the second and third stacks are performed by carrying out:
conformally depositing an overall active layer, a first part of the overall active layer extending opposite the side surface of the first upper electrode, the first part of the overall active layer being in electrical contact with the first upper electrode, a second part of the overall active layer extending opposite the side surface of the second upper electrode, the second part of the overall active layer being in electrical contact with the second upper electrode;
separating the overall active layer into at least said second active layer and said one third active layer, which are disjoint.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-16 are rejected under 35 U.S.C. 103 as being unpatentable over Ikarashi et al. (U.S. 2020/0052036 A1, hereinafter refer to Ikarashi) in view of Fricke et al. (U.S. 2004/0151024 A1, hereinafter refer to Fricke).
Regarding Claim 1: Ikarashi discloses an assembly including at least two selectors (10) electrically disposed in parallel with each other and each being electrically connected in series to a memory layer (40) forming at least two distinct non-volatile resistive memories each associated, respectively, with one of the two selectors (10) (see Ikarashi, Fig.19 as shown below and ¶ [0103]), the assembly including:
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- a first planar stack (see Ikarashi, Fig.19 as shown above), comprising:
a first active layer (40) which extends in parallel to a given horizontal plane (P), the first active layer (40) being said memory layer (see Ikarashi, Fig.19 as shown above); and
a first upper electrode (50) and a second upper electrode (50) which both extend on the first active layer (40) and which are electrically insulated from each other, the first upper electrode (50) being laterally delimited by a side surface, the second upper electrode (50) being laterally delimited by another side surface, an insulating layer (air gap, which is known as the best insulating layer (material)) extending between a part of the side surface of the first upper electrode (50) and a part of the side surface of the second upper electrode (50) to electrically insulate the first upper electrode (50) from the second upper electrode (50) (see Ikarashi, Fig.19 as shown above);
- a second stack, which extends obliquely or perpendicularly to said plane (P),comprising a second active layer (10), the second active layer (10) being in electrical contact with the first upper electrode (50), the second active layer (10) being a selective layer (see Ikarashi, Fig.19 as shown above);
- a third stack (10), which extends obliquely or perpendicularly to said plane (P),comprising a third active layer (10), the third active layer (10) being in electrical contact with the second upper electrode (50), the third active layer (10) being another selective layer (see Ikarashi, Fig.19 as shown above);
- the second and third active layers (10) being disjoint, with no direct electrical contact therebetween (see Ikarashi, Fig.19 as shown above).
Ikarashi is silent upon explicitly disclosing wherein at least a part of the second active layer extending opposite another part of the side surface of the first upper electrode;
at least a part of the third active layer extending opposite another part of the side surface of the second upper electrode.
For support see Fricke, which teaches wherein at least a part of the second active layer (25) extending opposite another part of the side surface of the first upper electrode (42/metal 2) (see Fricke, Fig.15 as shown below and ¶ [0002]);
at least a part of the third active layer (25) extending opposite another part of the side surface of the second upper electrode (42/metal 2) (see Fricke, Fig.15 as shown below and ¶ [0002]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Ikarashi and Fricke to enable the Ikarashi’s at least a part of the second active layer to extend opposite another part of the side surface of the first upper electrode and at least a part of the third active layer to extend opposite another part of the side surface of the second upper electrode as taught by Fricke in order to obtain a memory architectures that not only increase density, but the speed of data access as well.
Regarding Claim 2: Ikarashi as modified teaches an assembly as set forth in claim 1 as above. The combination of Ikarashi and Fricke further teaches wherein a lower electrode (BL), which extends beneath the first active layer (40), in parallel thereto, and which is in electrical contact with a lower face of the first active layer (40) (see Ikarashi, Fig.19 as shown above),
wherein at least a part of the first upper electrode (50) is located in vertical alignment with the lower electrode (BL), superimposed on the lower electrode (BL), in a projection along a direction perpendicular to said plane (see Ikarashi, Fig.19 as shown above), and
wherein at least a part of the second upper electrode (50) is located in vertical alignment with the lower electrode (BL), superimposed on the lower electrode (BL), in a projection along a direction perpendicular to said plane (see Ikarashi, Fig.19 as shown above).
Regarding Claim 3: Ikarashi as modified teaches an assembly as set forth in claim 2 as above. The combination of Ikarashi and Fricke further teaches wherein at least one of the upper electrodes (50) is only partially superimposed on the lower electrode (BL) (see Ikarashi, Fig.19 as shown above).
Regarding Claim 4: Ikarashi as modified teaches an assembly as set forth in claim 2 as above. The combination of Ikarashi and Fricke further teaches wherein: the first and second upper electrodes (50) are separated from each other, along a given horizontal direction, by a given spacing (see Ikarashi, Fig.19 as shown above), and wherein
along said direction, the first upper electrode (50) is superimposed on the lower electrode (BL) over a distance which is less than said spacing (see Ikarashi, Fig.19 as shown above).
Regarding Claim 5: Ikarashi as modified teaches an assembly as set forth in claim 2 as above. The combination of Ikarashi and Fricke further teaches wherein the first active layer (26) laterally extends beyond the lower electrode (20/metal 1), protruding on a dielectric layer (40/ILD) (see Fricke, Fig.15 as shown above).
Regarding Claim 6: Ikarashi as modified teaches an assembly as set forth in claim 1 as above. The combination of Ikarashi and Fricke further teaches wherein: the first active layer (40) is laterally delimited by a side surface (see Ikarashi, Fig.19 as shown above), and
the assembly further comprises an electrically insulating spacer (air gap) which extends at least against the side surface of the first active layer (40), at least partly covering this the side surface (see Ikarashi, Fig.19 as shown above).
Regarding Claim 7: Ikarashi as modified teaches an assembly as set forth in claim 6 as above. The combination of Ikarashi and Fricke further teaches wherein the spacer (air gap) also covers, only partly, the side surface of at least one of the first and second upper electrodes (50) (see Ikarashi, Fig.19 as shown above).
Regarding Claim 8: Ikarashi as modified teaches an assembly as set forth in claim 1 as above. The combination of Ikarashi and Fricke further teaches wherein the first and second upper electrodes (50) are in direct contact with the first active layer (40) (see Ikarashi, Fig.19 as shown above).
Regarding Claim 9: Ikarashi as modified teaches an assembly as set forth in claim 1 as above. The combination of Ikarashi and Fricke further teaches wherein the first planar stack comprises an insulating layer (Fig.15, 40/ILD, Fig.19, air gap) which extends above the first and second upper electrodes (Fig.15, 42/metal 2/Fig.19, 50) (see Fricke, Fig.15 as shown above and see Ikarashi, Fig.19 as shown above).
Regarding Claim 10: Ikarashi as modified teaches an assembly as set forth in claim 1 as above. The combination of Ikarashi and Fricke further teaches a fourth, planar, stack disposed on the insulating layer (air gap insulating layer) (see Ikarashi, Fig.19 as shown above), the fourth stack comprising:
a fourth active layer (40) which extends in parallel to said plane, the fourth active layer (40) being a memory layer (see Ikarashi, Fig.19 as shown above);
a third and a fourth electrode (50) which extend in parallel to said plane, between the fourth active layer (40) and the insulating layer (air gap insulating layer), and which are electrically insulated from each other, the third electrode (50) being laterally delimited by a side surface being laterally delimited by another side surface, an insulating layer extending between a part of the side surface of the third electrode (50) and a part of the side surface of the fourth electrode (50) to electrically insulate the third electrode from the fourth electrode (50) (see Ikarashi, Fig.19 as shown above);
wherein the second active layer (10) extends beyond the side surface of the first upper electrode (50), extending along a part of the side surface of the third electrode (50) (see Ikarashi, Fig.19 as shown above), and
wherein the third active layer (10) extends beyond the side surface of the second upper electrode (50) by extending along a part of the side surface of the fourth electrode (50) (see Ikarashi, Fig.19 as shown above).
Regarding Claim 11: Ikarashi as modified teaches an assembly as set forth in claim 10 as above. The combination of Ikarashi and Fricke further teaches wherein the fourth stack comprises:
a fifth electrode (BL), which extends above the fourth active layer (40), in electrical contact with the fourth active layer (40) (see Ikarashi, Fig.19 as shown above), and
an electrically insulating third spacer (air gap insulating layer) which covers a side surface of the fifth electrode (BL) (see Ikarashi, Fig.19 as shown above).
Regarding Claim 12: Ikarashi as modified teaches an assembly as set forth in claim 1 as above. The combination of Ikarashi and Fricke further teaches wherein the first active layer (40), common to the second and third stacks, is continuous, in one piece (see Ikarashi, Fig.19 as shown above).
Regarding Claim 13: Ikarashi as modified teaches an assembly as set forth in claim 1 as above. The combination of Ikarashi and Fricke further teaches wherein the first active layer (40) is divided into a first part and a second part, which are disjoint, the first part of the active layer (40) extending beneath the first upper electrode (50), the second part of the active layer (40) extending beneath the second upper electrode (50) (see Ikarashi, Fig.19 as shown above).
Regarding Claim 14: Ikarashi as modified teaches an assembly as set forth in claim 1 as above. The combination of Ikarashi and Fricke further teaches resistive memory array comprising a plurality of assemblies according to claim 1, wherein, for each assembly:
the first planar stack of the assembly is electrically connected to an addressing row of the array (see Ikarashi, Fig.19 as shown above),
the second and third vertical stacks of the assembly are electrically connected to two addressing columns of the array respectively, the two addressing columns being distinct (see Ikarashi, Fig.19 as shown above).
Regarding Claim 15: Ikarashi discloses a method for manufacturing an assembly comprising at least two selectors electrically disposed in parallel with each other and each electrically connected in series to a memory layer (40) forming at least two distinct non-volatile resistive memories each associated, respectively, with one of the two selectors (40), the method comprising (see Ikarashi, Fig.19 as shown above and ¶ [0103]):
- forming a first planar stack (see Ikarashi, Fig.19 as shown above) comprising:
depositing a first active layer (40) extending in parallel to a given horizontal plane (P), the first active layer being said memory layer (40) (see Ikarashi, Fig.19 as shown above); and
depositing a first upper electrode (50) and a second upper electrode (50) which both extend on the first active layer (40) and which are electrically insulated from each other, the first upper electrode (50) being laterally delimited by a side surface, the second upper electrode (50) being laterally delimited by another side surface, an insulating layer (air gap, which is known as the best insulating layer (material)) extending between a part of the side surface of the first upper electrode (50) and a part of the side surface of the second upper electrode (50) to electrically insulate the first upper electrode (50) from the second upper electrode (50) (see Ikarashi, Fig.19 as shown above);
- forming a second stack, which extends obliquely or perpendicularly to said plane (P), comprising a second active layer (10), the second active layer (10) being in electrical contact with the first upper electrode (50), the second active layer (10) being a selective layer (see Ikarashi, Fig.19 as shown above);
- forming a third stack, which extends obliquely or perpendicularly to said plane (P), comprising a third active layer (10), the third active layer (10) being in electrical contact with the second upper electrode (50), the third active layer (10) being another selective layer (see Ikarashi, Fig.19 as shown above).
Ikarashi is silent upon explicitly disclosing wherein at least a part of the second active layer extending opposite another part of the side surface of the first upper electrode,
at least a part of the third active layer extending opposite another part of the side surface of the second upper electrode.
For support see Fricke, which teaches wherein at least a part of the second active layer (25) extending opposite another part of the side surface of the first upper electrode (42/metal 2) (see Fricke, Fig.15 as shown above and ¶ [0002]);
at least a part of the third active layer (25) extending opposite another part of the side surface of the second upper electrode (42/metal 2) (see Fricke, Fig.15 as shown above and ¶ [0002]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Ikarashi and Fricke to enable the Ikarashi’s at least a part of the second active layer to extend opposite another part of the side surface of the first upper electrode and at least a part of the third active layer to extend opposite another part of the side surface of the second upper electrode as taught by Fricke in order to obtain a memory architectures that not only increase density, but the speed of data access as well.
Regarding Claim 16: Ikarashi as modified teaches a method for manufacturing an assembly as set forth in claim 15 as above. The combination of Ikarashi and Fricke further teaches wherein forming the second and third stacks are performed by carrying out (see Fricke, Fig.15 as shown above):
conformally depositing an overall active layer (25), a first part of the overall active layer (25) extending opposite the side surface of the first upper electrode (42/metal 2), the first part of the overall active layer (25) being in electrical contact with the first upper electrode (42/metal 2), a second part of the overall active layer (25) extending opposite the side surface of the second upper electrode (42/metal 2), the second part of the overall active layer (25) being in electrical contact with the second upper electrode (42/metal 2) (see Fricke, Fig.15 as shown above);
separating the overall active layer (25) into at least said second active layer (25) and said one third active layer (25), which are disjoint (see Fricke, Fig.15 as shown above).
Conclusion
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/BITEW A DINKE/ Primary Examiner, Art Unit 2812
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