DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1, 21, and 26 are objected to because of the following informalities:
Claim 1 line 1, the words “Voltage limiting device” should read – A voltage limiting device –
Claim 21 line 1, the words “constant current circuit” should read – a constant current circuit –
Claim 26 line 1, the words “Isolation transformer” should read – An isolation transformer –
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-8, 18, 21, and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jankowski Publication No. US 2015/0333509.
Regarding claims 1, 18, 21, Jankowski discloses a voltage limiting device for constant current circuits, the voltage limiting device comprising:
input terminals [Fig. 1-3; input terminals 12.1] for connecting the voltage limiting device to a current supply of a constant current circuit [current supply connected at the primary side of the transformer 10; par. 0070];
output terminals for connecting the voltage limiting device to a load [Fig. 1-3; load is connected at the output terminals of the secondary winding of the transformer],
wherein the voltage limiting device [Fig. 3, diode D1] is configured to have the input terminals connected to the output terminals under a normal operating condition, a voltage clamping circuit configured to clamp a voltage across the output terminals to a first voltage threshold [par. 0080-0084; par. 0090], and
a switching circuit [Fig. 3, 16, 18; par. 0095] configured to short-circuit the output terminals [par. 0079], the input terminals, or both the output terminals and the input terminals, when a second voltage threshold across the output terminals is exceeded for a predetermined time period [par. 0099, 0103].
Regarding claim 4, Jankowski discloses that the switching circuit comprises a delay logic [Fig. 3, comparator K] operably coupled to a switch device [Fig. 3, 18, transistors T1, T2], the delay logic configured to trigger the switch device at the predetermined time period [Fig. 3, the output of the comparator K controls the gates of the transistors T1, T2; par. 0095; the comparator can function as a delay logic circuit typically by leveraging inherent propagation delay].
Regarding claim 5, Jankowski comprises a voltage detection circuit [Fig. 3, R1, D2] configured to trigger the delay logic when a voltage across the output terminals exceeds the second voltage threshold [par. 0101].
Regarding claim 6, Jankowski discloses that the voltage detection circuit is configured to reset the delay logic when the voltage across the output terminals drops below the second voltage threshold [par. 100 indicates that the secondary circuit 10.1 is short circuited by using the control circuit 16 to trigger the switch 18, and the secondary side resets again when the positive input of the comparator K drops below the threshold].
Regarding claim 7, Jankowski discloses that the switching circuit comprises a semiconductor switch device and a relay circuit, wherein both the semiconductor switch device and the relay circuit are configured to short-circuit the output terminals and/or the input terminals [page 5, claim 5, “wherein the switch unit comprises one or more of the following components: at least one MOSFET; two MOSFETs arranged in a back-to-back circuit; a solid-state relay (SSR) with (i) a MOSFET, or (ii) a plurality of MOSFETs arranged in parallel; a TRIAC; an opto-isolator for introducing the control signal.”].
Regarding claim 8, Jankowski discloses that the switching circuit comprises a control unit operably coupled to the relay circuit and to the semiconductor switch device, wherein the control unit is implemented with a delay logic configured to trigger the semiconductor switch device and the relay circuit [Fig. 3, control unit 16; par. 0075, 0079].
Regarding claim 26, Jankowski discloses an isolation transformer [Fig. 1-2, current transformer 10] for use in a constant current circuit, the isolation transformer comprising a primary side having primary windings [par. 0013] and a secondary side having secondary windings and secondary terminals [par. 0014], wherein the isolation transformer further comprises: a voltage limiting device, wherein the input terminals of the voltage limiting device are connected to the secondary terminals,
wherein the voltage limiting device comprises:
input terminals [Fig. 1-3; input terminals 12.1] for connecting the voltage limiting device to a current supply of a constant current circuit [current supply connected at the primary side of the transformer 10; par. 0070];
output terminals for connecting the voltage limiting device to a load [Fig. 1-3; load is connected at the output terminals of the secondary winding of the transformer],
wherein the voltage limiting device [Fig. 3, diode D1] is configured to have the input terminals connected to the output terminals under a normal operating condition, a voltage clamping circuit configured to clamp a voltage across the output terminals to a first voltage threshold [par. 0080-0084; par. 0090], and
a switching circuit [Fig. 3, 16, 18; par. 0095] configured to short-circuit the output terminals [par. 0079], the input terminals, or both the output terminals and the input terminals, when a second voltage threshold across the output terminals is exceeded for a predetermined time period [par. 0099, 0103].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 11, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jankowski Publication No. US 2015/0333509.
Regarding claims 11 and 20, Jankowski discloses a comparator which has an inherent propagation delay, which is the time delay for a signal to pass from input to output. However, Jankowski does not explicitly disclose that the predetermined time period is between 50 ms and 2000 ms. It would have been obvious to one having ordinary skill in the art at the time of the filing of the invention to have the predetermined time period between 50 ms and 2000 ms, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claims 2, 19, Jankowski discloses that the first voltage clamping circuit [Fig. 3, Zener diode D1] starts clamping after a voltage exceeds a first threshold voltage and the second voltage protection circuit [Fig. 3, 16] gets activated after a voltage exceeds a second threshold voltage set by R1 and D2. However, Jankowski does not explicitly disclose that the first voltage threshold is higher than or equal to the second voltage threshold. It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to have the first voltage threshold higher than the second voltage threshold, for the benefit of avoiding false triggers or protect against potential damage from overloading the system.
Furthermore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have the first voltage threshold higher than the second voltage threshold, since it has been held that a mere reversal of the essential working parts of a device involves only routine skill in the art. In re Einstein, 8 USPQ 167.
Regarding claim 3, Jankowski does not explicitly disclose that the second voltage threshold is a voltage having one or a combination of: a root mean square value of 50 V or less and a peak value of 71 V or less. It would have been obvious to one having ordinary skill in the art at the time of the filing of the invention to have the second voltage threshold having one or a combination of: a root mean square value of 50 V or less and a peak value of 71 V or less, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Jankowski Publication No. US 2015/0333509, in view of Majewski et al. Publication No. US 2020/0292161.
Regarding claim 22, Jankowski discloses a load connected at the output terminals of the voltage limiting device. However, Jankowski does not further comprise one or more LED devices connected at the output terminals of the voltage limiting device.
Majewski discloses a constant current transformer [Fig. 1, transformer 11] comprising a primary side, a secondary side, and one or more LED devices [Fig. 1, 19] connected at the output terminals of the secondary side of the transformer.
Jankowski and Majewski are analogous constant current transformers. It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to incorporate Majewski’s LED load devices, into Jankowski, for the benefit of having a transformer that regulates voltage and preventing spikes that can cause overheating of the LEDs.
Allowable Subject Matter
Claims 9-10, 23-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance of claim 9: The prior art does not further comprise a monitoring circuit configured to test operation of the voltage clamping circuit. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
The following is an examiner’s statement of reasons for allowance of claim 23: The prior art does not disclose that the constant current circuit is configured to provide an AC current at the output terminals. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DHARTI PATEL whose telephone number is (571)272-8659. The examiner can normally be reached M - F 9 AM - 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and
https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
DHARTI PATEL
Primary Examiner
Art Unit 2836
/DHARTI H PATEL/Primary Examiner, Art Unit 2838