Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, and 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki (US 20030089991 A1), in further view of Miyamoto (US 20200185527 A1), and Jang (US 20220037420 A1).
Regarding independent claim 1, Yamazaki teaches a display device, comprising: a base substrate (Fig. 1, 101; [0123], “The substrate 101 comprises a glass substrate or an organic resin substrate.”); and a thin film transistor layer which is provided on the base substrate (Fig. 1, (While not labeled, there is a layer composed of TFTs); [0124], “As shown in FIG. 1, a n-channel type TFT 303 and p-channel type TFT 304 are formed in the driving circuit section 301, and a n-channel type first TFT 305, a p-channel type fourth TFT 306 and a capacity section 307 are formed in the pixel section 302.”), and in which a first semiconductor film made of polysilicon (Fig. 1, 103; [0122], “The semiconductor layer forming the channel forming region of the TFT may comprise amorphous silicon or polycrystalline silicon.”), a first inorganic insulating film (Fig. 1, 108; [0125], “…a gate insulation film 108…”), a first metal film (Fig. 1, 110; [0125], “…and gate electrodes 110 to 113.”, (Since the metal films in the present application become gate electrodes, this is a valid comparison)), a second inorganic insulating film (Fig. 1, 114; [0125], “A second inorganic insulation layer 114 comprising silicon nitride or silicon oxynitride containing hydrogen is formed on the gate electrode.”), a third inorganic insulating film (Fig. 1, 116; [0126], “The third inorganic insulation layer 116 must be a fine film…”, a second semiconductor film made of an oxide semiconductor (Fig. 1, 106), a fourth inorganic insulating film (Fig. 1,129; [0129], “The fourth inorganic insulation layer 129 is formed with an inorganic insulation material…”), are layered in this order, the thin film transistor layer including, for each of subpixels constituting a display region, a first thin film transistor including a first semiconductor layer formed by the first semiconductor film (Fig. 1, 304; [0124], “…p-channel type TFT 304…”), a second thin film transistor including a second semiconductor layer formed by the second semiconductor film (Fig. 1, 303; [0124], “…a n-channel type TFT 303…”), and a third thin film transistor including a third semiconductor layer formed by the second semiconductor film (Fig. 1, 305; [0124], “…and a n-channel type first TFT 305…”), and a first gate electrode provided overlapping the first channel region, on the first semiconductor layer, via the first inorganic insulating film, the first gate electrode being formed by the first metal film (Fig. 1, 111; [0125], “…and gate electrodes 110 to 113.”), a second gate electrode provided overlapping the second channel region, on the second semiconductor layer, via the fourth inorganic insulating film, the second gate electrode being formed by the third metal film (Fig. 1, 110; [0125], “…and gate electrodes 110 to 113.”), a fourth gate electrode provided overlapping the third channel region, on the third semiconductor layer, via the fourth inorganic insulating film, the fourth gate electrode being formed by the third metal film (Fig. 1, 112; [0125], “…and gate electrodes 110 to 113.”). However, Yamazaki does not teach a second metal film, a third metal film, and a third gate electrode provided overlapping the second channel region, on a side of the base substrate of the second semiconductor layer, via the third inorganic insulating film, the third gate electrode being formed by the second metal film, and a fifth gate electrode provided overlapping the third channel region, on a side of the base substrate of the third semiconductor layer, via the second inorganic insulating film and the third inorganic insulating film, the fifth gate electrode being formed by the first metal film; or wherein the first thin film transistor includes the first semiconductor layer including a first conductor region and a second conductor region defined to be separated from each other, and also including a first channel region defined between the first conductor region and the second conductor region, the second thin film transistor includes the second semiconductor layer including a third conductor region and a fourth conductor region defined to be separated from each other, and also including a second channel region defined between the third conductor region and the fourth conductor region, and the third thin film transistor includes the third semiconductor layer including a fifth conductor region and a sixth conductor region defined to be separated from each other, and also including a third channel region defined between the fifth conductor region and the sixth conductor region.
However, in the same field of endeavor, Miyamoto teaches a second metal film (Fig. 1, 19; [0047], “…a second metal film (second electrically conductive film) 19…”), a third metal film (Fig. 1, 20; [0047], “…a third metal film (third electrically conductive film) 21…”), and a gate electrode provided overlapping the second channel region, on a side of the base substrate of a semiconductor layer, via an inorganic insulating film, the gate electrode being formed by a metal film (Fig. 6, 30a; [Abstract], “A gate driver TFT 30 includes a first gate electrode 30a formed from a first metal film 15, a second gate electrode 31 formed from a second metal film 19 and overlapping a part of the first gate electrode 30a…”, (In this art, there are two gate electrodes overlapping each other with a semiconductor layer between them. This corresponds to the second and third TFTs in the present application, which each have two gate electrodes in this configuration, as stated in the paragraph above.)), and Jang teaches wherein a thin film transistor includes a semiconductor layer including a first conductor region and a second conductor region defined to be separated from each other, and also including a channel region defined between the first conductor region and the second conductor region ([0161], “The semiconductor pattern SCP may include a channel region overlapping each gate electrode GE, and first and second conductive regions (e.g., source and drain regions) disposed at both sides of the channel region.” (Since multiple TFTs in the present application have this structure, this art speaks for that structure in general and can be applied to all of them discussed in the application.)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display device of Yamazaki with the metal layers and associated gate electrode structures of Miyamoto so as to “increase the breakdown voltage of the thin-film transistor” (Miyamoto, [0007], and the semiconductor structure of Jang so as to implement source and drain regions (Jang, [0161]).
Regarding dependent claim 4, Yamazaki, as previously modified by Miyamoto and Jang, teaches the display device according to claim 1, and further teaches wherein the base substrate is a resin substrate (Fig. 1, 101; [0123], “The substrate 101 comprises a glass substrate or an organic resin substrate.”), a base coat film is provided on the resin substrate (Fig. 1, 102; [0125], “…in combination with the first inorganic insulation layer 102 serves as a protective film which prevents contamination of the semiconductor layers caused by diffusion of impurities such as moisture or metal into the semiconductor layers.”), and the first semiconductor film is provided on the base coat film ([0125], “These TFTs comprise semiconductor layers 103 to 106 on the first inorganic insulation layer 102…”).
Regarding dependent claim 5, Yamazaki, as previously modified by Miyamoto and Jang, teaches the display device according to claim 1, and further teaches further comprising: a light-emitting element layer provided on the thin film transistor layer and provided with a plurality of light-emitting elements arrayed (Fig. 1, 309; [0127], “The organic light emitting element 309 is formed on the third inorganic insulation layer 116.”); and a sealing film provided covering each of the plurality of light-emitting element layers (Fig. 1, 133, 134; [0135], “A sealing plate 134 is secured via the seal patterns 133.”).
Regarding dependent claim 6, Yamazaki, as previously modified by Miyamoto and Jang, teaches the display device according to claim 5, and further teaches wherein each of the plurality of light-emitting elements is an organic electroluminescence element (Fig. 1, 309; [0127], “The organic light emitting element 309 is formed on the third inorganic insulation layer 116.”).
Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki (US 20030089991 A1), in further view of Miyamoto (US 20200185527 A1), Jang (US 20220037420 A1), and Okabe (US 20210036093 A1).
Regarding dependent claim 2, Yamazaki, as previously modified by Miyamoto and Jang, teaches the display device according to claim 1. However, as previously combined, they do not teach wherein the first thin film transistor is provided to constitute a write control thin film transistor, a drive thin film transistor, a power supply control thin film transistor, or a light emission control thin film transistor, the second thin film transistor is provided to constitute a first initialization thin film transistor configured to reset an electric charge accumulated in a capacitor, or to constitute a threshold voltage compensation thin film transistor, and the third thin film transistor is provided to constitute a second initialization thin film transistor configured to reset an electric charge accumulated in an anode electrode.
However, in the same field of endeavor, Okabe teaches wherein the first thin film transistor is provided to constitute a write control thin film transistor, a drive thin film transistor, a power supply control thin film transistor, or a light emission control thin film transistor (Fig. 7, T1-7; [0058], “In one example illustrated in FIG. 7, the subpixel circuit includes an initialization transistor T1, a threshold voltage compensation transistor T2, a write control transistor T3, a drive transistor T4, a power supply control transistor T5, a light emission control transistor T6, and an anode electrode charge discharge transistor T7 formed in the TFT layer 4.”), the second thin film transistor is provided to constitute a first initialization thin film transistor configured to reset an electric charge accumulated in a capacitor, or to constitute a threshold voltage compensation thin film transistor (Fig. 7, T2; [0058], “…a threshold voltage compensation transistor T2…”), and the third thin film transistor is provided to constitute a second initialization thin film transistor configured to reset an electric charge accumulated in an anode electrode (Fig. 7, T7; [0058], “…and an anode electrode charge discharge transistor T7”.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display device as described by the combination of Yamazaki, Miyamoto, and Jang with the transistor types of Okabe so as to “display high-quality image with no influence of noise.” (Okabe, [0006]).
Regarding dependent claim 3, Yamazaki, as previously modified by Miyamoto and Jang, teaches the display device according to claim 1. However, as previously combined, they do not teach wherein a plurality of light emission control lines extending in parallel with each other are provided in the display region, and each of the plurality of light emission control lines is formed by the first metal film and the third metal film.
However, in the same field of endeavor, Okabe teaches wherein a plurality of light emission control lines extending in parallel with each other are provided in the display region (Fig. 8, EM; [0092], “…the plurality of light emission control lines EM provided in the display area DA…”), and each of the plurality of light emission control lines is formed by the first metal film and the third metal film ([0027], “…the light emission control line EM…are each formed of a single layer film or a layered film of metal…”).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display device as described by the combination of Yamazaki, Miyamoto, and Jang with the light emission control lines of Okabe so as to control light emission (“According to a display device of a ninth aspect of the present invention, in the fifth to eighth aspects, the display area may be provided with a plurality of data signal lines configured to supply a data signal to the plurality of subpixels, a plurality of gate lines configured to scan the plurality of subpixels, and a plurality of light emission control lines…”, (The lack of a description for the light emission control lines compared to the other lines means that their function is self-explanatory), Okabe, [0154]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20030129790 A1, pertaining to a similar display device.
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/TIMOTHY JAMES MATTABONI/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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