Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/28/2025 & 06/20/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7-19 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding claim 7, Regarding claim 7, the claim recites “said signal processing unit on the Nth said data processing layer of M said data processing layers corresponds to at least one said signal processing unit on the N−1th said data processing layer, and said signal processing unit on the Nth said data processing layer corresponds to and is electrically connected to one said signal processing unit on a N+1th said data processing layer, wherein 1≤N≤M, and N is an integer.” However, when N = M, the claimed “N+1th said data processing layer” would correspond to an M+1th data processing layer, which is not present because the claim only recites M data processing layers. The specification does not resolve this ambiguity. Rather, the specification describes only one probe layer 11 and M data processing layers 12 stacked sequentially from bottom to top (see original specification [0066]) and further describes that when M>1, the probe device includes one probe layer 11 and M data processing layers 12 stacked sequentially from bottom to top (see [0070]). Thus, the specification confirms that there are only M data processing layers, and does not describe an additional M+1th data processing layer. Therefore, the metes and bounds of the claimed inter-layer correspondence and electrical connection are unclear.
Additionally, claim 7 also recites that the signal processing unit on the Nth data processing layer corresponds to at least one signal processing unit on the N−1th data processing layer, wherein 1≤N≤M. However, when N = 1, the claimed N−1th data processing layer would correspond to a 0th data processing layer, which is not clearly defined in the claim. The specification explains that the first data processing layer 12 is adjacent to the probe layer 11 and corresponds to probes 20 on the probe layer (see [0067]), but the specification does not identify a 0th data processing layer. Therefore, the claim is unclear as to the correspondence relationship for the first data processing layer.
Regarding claim 13, the claim recites “when 1≤N<M, for each said signal processing unit on a Nth said data processing layer of the M said data processing layers, said signal processing unit is electrically connected to a target signal processing unit in the N+1th said data processing layer by means of conductive materials in the corresponding through-holes.” The claim further recites “When N=1, for each said signal processing unit on the first said data processing layer of the M said data processing layers, said signal processing unit is electrically connected to a target probe on said probe layer by means of the conductive substances in the corresponding through-holes.” Because N=1 falls within the range 1≤N<M when M>1, it is unclear whether the signal processing unit on the first data processing layer must be electrically connected to both a target signal processing unit in the N+1th data processing layer and a target probe on the probe layer, or whether one of the recited conditions was intended to exclude the other. The specification does not clearly resolve the ambiguity because it describes that signal processing units on the first data processing layer correspond to probes on the probe layer ([0067]), but also describes interconnection between signal processing units on adjacent data processing layers (see [0068] & [0071]). Further, the specification’s description of the through-hole embodiment contains inconsistent layer-numbering language, stating “when 1≤N<M” for connection to the N+1th data processing layer, but also stating “when N=M” for connection to a target probe on the probe layer (see [0100]), while the claim recites “When N=1” for connection to the target probe. Therefore, the scope of the claimed electrical connection arrangement is unclear.
Regarding claim 14, the claim recites “when 1≤N<M, for each said signal processing unit on a Nth said data processing layer of the M said data processing layers, said signal processing unit is electrically connected to a target signal processing unit in a N+1th said data processing layer by means of leads passing through the corresponding through-holes.” The claim further recites “When N=1, for each said signal processing unit on the first said data processing layer of the M said data processing layers, said signal processing unit is electrically connected to a target probe on said probe layer by means of leads passing through the corresponding through-holes.” Because N=1 falls within the range 1≤N<M when M>1, it is unclear whether the signal processing unit on the first data processing layer must be electrically connected to both a target signal processing unit in the N+1th data processing layer and a target probe on the probe layer, or whether one of the recited conditions was intended to exclude the other. The specification does not clearly resolve this issue. The specification explains that the first data processing layer adjacent to the probe layer is electrically connected to corresponding probes (see [0067]) and also explains that signal processing units on different data processing layers are electrically connected in a hierarchical relationship (see [0068] & [0071]). In addition, the lead-through-hole embodiment states that when 1≤N<M, a signal processing unit on the Nth data processing layer is electrically connected to a target signal processing unit in the N+1th data processing layer by leads, and when N=1, a signal processing unit on the Nth data processing layer is electrically connected to a target probe on the probe layer by leads (see [0101]). Since the specification repeats the same overlapping condition, the specification does not clarify whether both electrical connections are required for the first data processing layer or whether one condition was intended to be excluded. Therefore, the scope of the claimed lead-based electrical connection arrangement is unclear.
Regarding claim 17, the claim recites “said signal processing unit is used to send the received probe data signal to the corresponding signal processing unit in a target functional layer; said target functional layer is said data processing layer previous to said data processing layer in which said signal processing unit is located.” The phrase “previous to said data processing layer” is unclear because the claim does not define whether the previous data processing layer is the immediately lower layer, the immediately upper layer, the prior layer in the stacking sequence from bottom to top, or the prior layer in the signal transmission direction. The specification does not resolve this ambiguity. The specification describes the data processing layers as stacked “from bottom to top” (see [0066] & [0070]) and describes that probe control signals are sent from the M-th data processing layer down through intermediate data processing layers to the first data processing layer and then to the probes (see [0074]). However, the specification also describes probe data signals being sent from the probes to the first data processing layer and then to the M-th data processing layer (see [0075] & [0077]). Thus, the direction of signal transmission depends on whether the signals are control signals or probe data signals. The phrase “previous to” does not clearly identify the target layer in either direction. Further, if the signal processing unit is located on the first data processing layer, the “previous” data processing layer is unclear because the layer adjacent to the first data processing layer may be the probe layer, not another data processing layer (see [0067]). Therefore, the scope of the claimed target functional layer and the direction of signal transmission are unclear.
Claims 8-12, 15-16, and 18-19 depend from claim 7 and are rejected for at least the same reasons set forth above because they incorporate the indefinite limitations of claim 7. In addition, claims 8-10 further depend on the unclear multilayer signal-processing relationship of claim 7, and the specification confirms that probe data signals may be sent from the first data processing layer to the M-th data processing layer and processed or stored at different layers (see [0077]–[0080]), but the base claim does not clearly define the layer-indexing relationship for all values of N. Claims 13 and 14 are separately indefinite for the additional reasons set forth above. Claims 15-16 and 18-19 are indefinite by dependency from claim 7 because they depend from claim 7 and therefore include the unclear layer correspondence and electrical connection limitations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1–3, 5–6 & 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Horiuchi et al. (U.S. 2015/0137849 A1) in view of Taguchi et al. (U.S. 2013/0169305 A1).
Regarding claim 1, Horiuchi et al. disclose a probe device wherein it comprises: a functional layer, a plurality of probes, and at least one signal processing unit (probe card 20 includes substrate 30, wiring substrate 40, conductive wires W1 electrically connecting the substrate 30 and wiring substrate 40; under BRI, substrate/wiring substrate corresponds to the functional layer and tester-interface circuitry corresponds to the signal processing unit, [0029]); said plurality of probes are provided on one surface of said functional layer (probe card 20 includes contact terminals 33 on the terminal layout surface facing the test subject 70, [0026]); and said at least one signal processing unit is provided on the other surface of said functional layer (wiring patterns 32 are formed on upper surface 31B of insulation layer 31, opposite the contact terminals 33, [0034]); each said signal processing unit corresponds to at least one said probe, and each said probe corresponds to and is electrically connected to one said signal processing unit (wiring patterns 32 include connection portions connected to contact terminals 33 and pads 37/38 for electrical connection, [0038]); said signal processing unit is used to generate a probe control signal according to control parameters input by a user and send said probe control signal to the corresponding probe (tester 10 is connected to probe card 20 for testing test subject 70 through the probe card, [0023]); said probe is used to operate and process the surface to be operated according to said probe control signal received, and to send probe data signals obtained to the corresponding signal processing unit (contact terminals 33 contact electrode pads 70P for electrical connection during testing, [0063]).
Horiuchi et al. are not understood to explicitly disclose the signal processing unit as generating a probe control signal according to control parameters input by a user.
Taguchi et al. disclose a probe card in which a signal of the measuring instrument is transmitted to the semiconductor wafer through main board 4, wiring board 3, and probe head 2, and a signal of the semiconductor wafer is transmitted to the measuring instrument in the reverse direction ([0060]).
It would have been obvious to one of ordinary skill in the art to modify Horiuchi’s probe card/tester arrangement by incorporating Taguchi’s probe-card signal transmission architecture because doing so provides a predictable signal path for transmitting test/control signals to the probes and returning probe/test signals from the semiconductor wafer to the measuring instrument ([0060]).
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Regarding claim 2, Horiuchi et al. disclose the probe device according to claim 1, wherein said functional layer is provided with a plurality of through-holes therein (insulation layer 31 includes through holes 31X extending through insulation layer 31 in the thickness wise direction, [0033]); said through-holes are provided with conductive substances therein (each contact terminal 33 includes via 33A located in through hole 31X and projection 33B projecting downward from lower surface 31A, [0035]); each said signal processing unit corresponds to at least one said through-hole, and each said through-hole corresponds to one said signal processing unit (each wiring pattern 32 includes a connection portion connected to one of the contact terminals 33 and a pad for electrical connection, [0038]); said signal processing unit is electrically connected to a target probe through the conductive substances in the corresponding through-holes (contact terminal 33 is connected to wiring pattern 32 through the corresponding through hole 31X, [0035]); said target probe is said probe corresponding to said signal processing unit (contact terminals 33 are formed at locations corresponding to electrode pads 70P of the test subject 70, [0036]).
Horiuchi et al. are not understood to explicitly disclose the through-holes as being provided with insulating layers on inner walls thereof in the same manner claimed.
Taguchi et al. disclose through hole T penetrating substrate 12, through hole conductor 13 formed on an inner wall of through hole T, and insulator 14 arranged inside through hole conductor 13 ([0029]).
It would have been obvious to one of ordinary skill in the art to modify Horiuchi’s through-hole/contact-terminal structure by incorporating Taguchi’s through-hole conductor and insulator arrangement because both references relate to probe-card/wiring-board electrical connection structures, and Taguchi’s arrangement provides a predictable electrical interconnection through an insulating board structure ([0029]).
Regarding claim 3, Horiuchi et al. & Taguchi et al. disclose the probe device according to claim 1, wherein Horiuchi et al. further disclose functional layer is provided with a plurality of through-holes therein (insulation layer 31 includes through holes 31X extending through insulation layer 31 in the thickness wise direction, [0033]); each said signal processing unit corresponds to at least one said through-hole, and each said through-hole corresponds to one said signal processing unit (each wiring pattern 32 includes a connection portion connected to one of the contact terminals 33 and a pad for electrical connection, [0038]); said signal processing unit is electrically connected to a target probe by means of leads passing through the corresponding through-holes (conductive wires W1 electrically connect pads 32P to connection pads 41P, 42P, 43P, and 44P; under BRI, conductive wires correspond to leads for electrical connection, [0059]); and said target probe is said probe corresponding to said signal processing unit (contact terminals 33 are formed at locations corresponding to electrode pads 70P of the test subject 70, [0036]); wherein leads passing through corresponding through-holes having insulating layers on inner walls thereof (see [0090]).
Regarding claim 5, Horiuchi et al. & Taguchi et al. disclose the probe device according to claim 1, wherein Horiuchi et al. further disclose functional layer is any one of the following: a silicon wafer, a glass wafer, a quartz wafer, a wafer or a printed circuit board (wiring substrate 40 is a multilayer wiring substrate including wiring layers and interlayer insulation layers, [0045]); wherein the functional layer is specifically a printed circuit board (see [0059]).
Regarding claim 6, Horiuchi et al. & Taguchi et al. disclose the probe device according to claim 1, wherein Horiuchi et al. further disclose each said probe has a corresponding address and any two said probes correspond to different addresses, respectively (electrode pads 70P are laid out in a matrix-like array, and contact terminals 33 are formed at locations corresponding to electrode pads 70P; under BRI, each contact terminal has a corresponding spatial/electrical address, [0036]); wherein each probe has a corresponding address and that any two probes correspond to different addresses (see [0063 & 0089]).
Regarding claim 20, Horiuchi et al. & Taguchi et al. disclose the probe device according to claim 1, wherein Horiuchi et al. further disclose a probe control system connected to said probe device (semiconductor testing device includes tester 10 and probe card 20 connected to tester 10, see [0029 & 0089]).
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 7-19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
In terms of claim 4, the prior art of record does not teach alone or in combination of “wherein said probe comprises: a needle, a cantilever beam and a needle tip, and in each said probe, said needle tip is provided at the tip portion of said needle, said needle is fixed at one end of said cantilever beam, and said cantilever beam, which is at the end away from said needle, comprises: a control input terminal and a signal output terminal; said signal processing unit comprising a control output terminal and a signal input terminal, said control input terminal of said cantilever beam is connected to the control output terminal of the corresponding signal processing unit, said signal output terminal of said cantilever beam is connected to the signal input terminal of the corresponding signal processing unit; said probe is used to control said needle tip to operate and process the surface to be operated according to said probe control signal received from said control input, and to send the obtained probe data signal to the signal input terminal of said signal processing unit connected thereto” in combination with all elements of claim 1.
Regarding claim 7, the prior art of record, including Horiuchi et al. and Taguchi et al., teaches probe-card structures having probes/contact terminals, wiring substrates, multilayer wiring boards, conductive vias, and signal transmission paths between a tester or measuring instrument and a semiconductor wafer. For example, Horiuchi et al. teach a probe card including substrate 30, wiring substrate 40, contact terminals 33, wiring patterns 32, conductive wires W1, and wiring layers 41-45 for electrically connecting the tester 10 to the test subject 70. Taguchi et al. teach a probe card including probe head 2, wiring board 3, main board 4, and signal transmission from a measuring instrument to a semiconductor wafer through the main board 4, wiring board 3, and probe head 2, and signal transmission back to the measuring instrument in the reverse direction.
However, the prior art of record does not teach or reasonably suggest the claimed multilayer probe device arrangement recited in claim 7, particularly “a plurality of functional layers fixed in a non-contact manner,” wherein “said plurality of functional layers comprise one probe layer and M data processing layers stacked sequentially from bottom to top,” and wherein “said plurality of signal processing units are provided on said data processing layers, respectively.” Although Horiuchi et al. and Taguchi et al. disclose multilayer wiring structures and signal routing paths, the references do not disclose a probe layer and one or more data processing layers arranged as claimed, with signal processing units provided on the data processing layers rather than merely passive wiring layers, vias, pads, or conductive traces.
Further, the prior art of record does not teach or reasonably suggest the claimed correspondence relationship in which “each said signal processing unit on a first said data processing layer corresponds to at least one said probe, and each said probe corresponds to and is electrically connected to one said signal processing unit located on the first said data processing layer.” Horiuchi et al. teach contact terminals connected to wiring patterns and wiring layers, and Taguchi et al. teach probes connected through a wiring board and main board. However, neither reference teaches the claimed one-to-one or one-to-many correspondence between probes and signal processing units located specifically on a first data processing layer.
Further, the prior art of record does not teach or reasonably suggest the claimed hierarchical relationship between signal processing units on different data processing layers, wherein “said signal processing unit on the Nth said data processing layer of M said data processing layers corresponds to at least one said signal processing unit on the N−1th said data processing layer,” and wherein “said signal processing unit on the Nth said data processing layer corresponds to and is electrically connected to one said signal processing unit on a N+1th said data processing layer.” Horiuchi et al. and Taguchi et al. disclose multilayer electrical interconnections, but the disclosed structures are directed to wiring layers, vias, conductive wires, and board-level routing, not a hierarchy of signal processing units arranged on multiple data processing layers with the claimed correspondence relationship.
Further, the prior art of record does not teach or reasonably suggest that “said probe device is used to receive input control parameters through said signal processing unit on at least one said data processing layer and generate probe control signals for said probes,” and that “said probe device is used to send said probe control signals to the corresponding probes via said signal processing unit on a first said data processing layer.” Horiuchi et al. and Taguchi et al. disclose transmission of testing signals through a probe card, but they do not disclose the claimed probe device receiving input control parameters through a signal processing unit on a data processing layer, generating probe control signals for corresponding probes, and sending those probe control signals through a first data processing layer having corresponding signal processing units.
Accordingly, if claim 7 is rewritten or amended to overcome the indefiniteness issue under 35 U.S.C. 112(b), the prior art of record would not teach or suggest the claimed combination of a probe layer, one or more data processing layers, signal processing units arranged on the data processing layers, hierarchical correspondence between signal processing units on adjacent data processing layers, and generation/transmission of probe control signals through the claimed data processing layer structure.
Claims 8-19 would be allowable for at least the same reasons, provided that such claims are rewritten or amended to overcome the 35 U.S.C. 112(b) rejection and include all limitations of the base claim and any intervening claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance."
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. 2013/0162276 A1 to Lee et al. disclose a probe card including a plurality of unit plates including pad areas and contact probe areas, a plurality of electrode pads formed in the pad areas, a plurality of contact probes formed in the contact probe areas, and a plurality of interconnecting layers electrically connecting the electrode pads and the contact probes. The plurality of unit plates has different sizes and are arranged and laminated so as to expose all the pad areas of each unit plate.
U.S. 2010/0327896 A1 to Lee discloses a probe assembly has insertion holes formed in a base layer provided on a circuit board. Probe pins are inserted into the insertion holes and fixed by a conductive adhesive filled in the insertion holes. The probe pins can be arranged with small pitch without mechanically electrically interfering with neighboring pins using the insertion holes. Furthermore, the base layer is formed of a semiconductor material to prevent a problem caused by a difference in the coefficient of thermal expansion between the base layer and a wafer. Moreover, coplanarity and alignment accuracy of the probe pins can be improved using aligning mask layers or aligning mask in a process of manufacturing the probe assembly. In addition, probe assembly manufacturing time can be reduced by using a pin array frame into which a large number of probe pins are temporarily inserted.
U.S. 2010/0026331 A1 to Chong et al. disclose a microfabricated spring contact structures and associated methods, e.g. such as for electrical contractors and interposers, comprise improvements to spring structures that extend from the substrate surface, and/or improvements to structures on or within the support substrate. Improved spring structures and processes comprise embodiments having selectively formed and etched, coated and/or plated regions, which are optionally further processed through planarization and/or annulment. Enhanced solder connections and associated processes provide a gap between substrates for componentry, and or improved manufacturing techniques using distributed spacers. Enhanced probe card assembly structures and processes provide improved planarization adjustment and thermal stability.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRUNG NGUYEN whose telephone number is (571)272-1966. The examiner can normally be reached on Mon- Friday 8AM - 4:00PM Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached on 571-272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Examiner: /Trung Q. Nguyen/- Art 2858
May 5, 2026
/HUY Q PHAN/Supervisory Patent Examiner, Art Unit 2858
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