Prosecution Insights
Last updated: July 17, 2026
Application No. 18/722,590

DISPLAY DEVICE

Non-Final OA §103
Filed
Jun 21, 2024
Priority
Feb 21, 2022 — nonprovisional of PCTJP2022006944
Examiner
MATTABONI, TIMOTHY JAMES
Art Unit
Tech Center
Assignee
Sharp Display Technology Corporation
OA Round
1 (Non-Final)
Grant Probability
Favorable
1-2
OA Rounds

Examiner Intelligence

Grants only 0% of cases
0%
Career Allowance Rate
0 granted / 0 resolved
-60.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
Avg Prosecution
26 currently pending
Career history
4
Total Applications
across all art units

Statute-Specific Performance

§103
100.0%
+60.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 0 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 2, and 8-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hotta (US 20050237441 A1), in further view of Yamazaki (US 20030089991 A1), Miyamoto (US 20200185527 A1) and Li (US 20190189779 A1). Regarding independent claim 1, Hotta teaches a display device, comprising: a base substrate (Fig. 1A, 100; [0065], “As shown in FIG. 1A, on a transparent insulating substrate 100 such as a glass substrate…”); and a thin film transistor layer provided on the base substrate (Fig. 1L, 103-111; [0081], “With this process, wiring lines 109s, 109d and the like are formed to lead upward each transistor region…”), the thin film transistor layer including a first semiconductor film made of polysilicon ([0065], “A polysilicon film may be deposited directly on the buffer layer 101.”), a first inorganic insulating film (Fig. 1C, 103; [0069], “As shown in FIG. 1C, an SiO layer of 30 nm in thickness is deposited covering the patterned island semiconductor layers by CVD to form a first gate insulating film 103.”), a first metal film (Fig. 1D, 104F; [0070], “…a wiring layer 104f is patterned which is used as a liner wiring layer of a gate wiring line…”), a second metal film (Fig. 1D, 104a, 104b; [0070], “In the thin film TFT area a gate electrode 104a and a gate electrode 104b are patterned…”), wherein the thin film transistor layer is provided with a first thin film transistor including a first semiconductor layer formed of the first semiconductor film (Fig. 1B, 102a,b; [0067], “Island semiconductor layers 102a and 102b are used for thin film TFTs…”), and a first gate electrode provided on the first semiconductor layer via the first inorganic insulating film and formed of a layered film of the first metal film and the second metal film (Fig. 1D, 104a,b; [0070], “In the thin film TFT area a gate electrode 104a and a gate electrode 104b are patterned…”), the first thin film transistor includes the first semiconductor layer including a first conductor region and a second conductor region defined to be separated from each other and a first channel region defined between the first conductor region and the second conductor region (Fig. 2, 102a,b; [0068], “As shown in FIG. 2, in each pixel area of a display area, the island semiconductor layer 102d for a pixel transistor is formed having broadened source/drain regions at opposite positions and a narrow channel region at a middle position.”), the second thin film transistor includes the second semiconductor layer including a third conductor region and a fourth conductor region defined to be separated from each other and a second channel region defined between the third conductor region and the fourth conductor region (Fig. 2, 102a,b; [0068], “As shown in FIG. 2, in each pixel area of a display area, the island semiconductor layer 102d for a pixel transistor is formed having broadened source/drain regions at opposite positions and a narrow channel region at a middle position.”), and the first semiconductor layer is provided with a low-concentration impurity region having an impurity concentration lower than an impurity concentration of each of the first conductor region and the second conductor region in such a manner as to overlap a portion of the thin film electrode portion protruding from the thick film electrode portion ((While the thin film electrode portion is not mentioned here, it will be included later with another source), [0017], “The other ion implantation is performed under the condition which allows some of the ions implanted into the insulating film 103 to pass through the insulating film 103 and reach the semiconductor layer 102 to form ion implanted regions of a low impurity concentration."). However, Hotta does not teach a second inorganic insulating film, a second semiconductor film made of an oxide semiconductor, a third inorganic insulating film, and a third metal film sequentially layered, and a second thin film transistor including a second semiconductor layer formed of the second semiconductor film for each subpixel constituting a display region, and a second gate electrode provided on the second semiconductor layer via the third inorganic insulating film and formed of the third metal film, and the first gate electrode includes a thick film electrode portion formed of a thicker one of the first metal film and the second metal film, and a thin film electrode portion formed of a thinner one of the first metal film and the second metal film in such a manner as to overlap the thick film electrode portion and protrude from the thick film electrode portion toward at least one side in a channel length direction. However, in the same field of endeavor, Yamazaki teaches a second inorganic insulating film (Fig. 1, 114; [0125], “A second inorganic insulation layer 114 comprising silicon nitride or silicon oxynitride containing hydrogen is formed on the gate electrode.”), a second semiconductor film made of an oxide semiconductor (Fig. 1, 106), a third inorganic insulating film (Fig. 1, 116; [0126], “The third inorganic insulation layer 116 must be a fine film…”), and a second thin film transistor including a second semiconductor layer formed of the second semiconductor film for each subpixel constituting a display region (Fig. 1, 303; [0124], “…a n-channel type TFT 303…”), and a second gate electrode provided on the second semiconductor layer via the third inorganic insulating film (Fig. 1, 110; [0125], “…and gate electrodes 110 to 113.”), Miyamoto teaches and a third metal film (Fig. 1, 20; [0047], “…a third metal film (third electrically conductive film) 21…”), and Li teaches and the first gate electrode includes a thick film electrode portion (Fig. 2k, 142), and a thin film electrode portion formed of a thinner one of the first metal film and the second metal film in such a manner as to overlap the thick film electrode portion and protrude from the thick film electrode portion toward at least one side in a channel length direction (Fig. 2k, 144, 142; [0019], “In one embodiment, the gate electrode 144 is aligned to an outer edge of the dual gate dielectric 142 and extends laterally over the dual gate dielectric 142…”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display device of Hotta with the films of Yamazaki so as to “improve the reliability of a light emitting apparatus” (Yamazaki, [0012]) , the metal film of Miyamoto so as to “increase the breakdown voltage of the thin-film transistor” (Miyamoto, [0007]), and the thin and thick electrode portions of Li so as to form “an active transistor gate” (Li, [0057]). Regarding dependent claim 2, Hotta, as previously modified by Yamazaki, Miyamoto, and Li, teaches the display device of claim 1. Li further teaches wherein the thick film electrode portion is formed of the first metal film, and the thin film electrode portion is formed of the second metal film and is provided covering one end portion of the thick film electrode portion in a channel length direction. (Fig. 2k, 144, 142; [0019], “In one embodiment, the gate electrode 144 is aligned to an outer edge of the dual gate dielectric 142 and extends laterally over the dual gate dielectric 142…”). Regarding dependent claim 8, Hotta, as previously modified by Yamazaki, Miyamoto, and Li, teaches the display device of claim 1. However, as previously combined, they do not teach wherein the base substrate is made of an organic resin material. However, Yamazaki further teaches wherein the base substrate is made of an organic resin material (Fig. 1, 101; [0123], “The substrate 101 comprises a glass substrate or an organic resin substrate.”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display device as described by the combination of Hotta, Yamazaki, Miyamoto, and Li with the resin substrate of Yamazaki so as to “reduce the weight of the light emitting apparatus” (Yamazaki, [0123]). Regarding dependent claim 9, Hotta, as previously modified by Yamazaki, Miyamoto, and Li, teaches the display device according to claim 8. However, as previously combined, they do not teach wherein a base coat film is provided on the base substrate, and the first semiconductor layer is provided on the base coat film. However, Yamazaki further teaches wherein a base coat film is provided on the base substrate (Fig. 1, 102; [0125], “…in combination with the first inorganic insulation layer 102 serves as a protective film which prevents contamination of the semiconductor layers caused by diffusion of impurities such as moisture or metal into the semiconductor layers.”), and the first semiconductor layer is provided on the base coat film ([0125],“These TFTs comprise semiconductor layers 103 to 106 on the first inorganic insulation layer 102…”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display device as described by the combination of Hotta, Yamazaki, Miyamoto, and Li with the base coat of Yamazaki so as to “prevent contamination of the semiconductor layers” (Yamazaki, [0125]). Regarding dependent claim 10, Hotta, as previously modified by Yamazaki, Miyamoto, and Li, teaches the display device according to claim 1. However, as previously combined, they do not teach further comprising: a light-emitting element layer provided on the thin film transistor layer and including a plurality of light-emitting elements being arrayed; and a sealing film provided on the light-emitting element layer. However, Yamazaki further teaches a light-emitting element layer provided on the thin film transistor layer and including a plurality of light-emitting elements being arrayed (Fig. 1, 309; [0127], “The organic light emitting element 309 is formed on the third inorganic insulation layer 116.”); and a sealing film provided on the light-emitting element layer (Fig. 1, 133, 134; [0135], “A sealing plate 134 is secured via the seal patterns 133.”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display device as described by the combination of Hotta, Yamazaki, Miyamoto, and Li with the light-emitting layer and sealing layer of Yamazaki so as to emit light through the substrate (Yamazaki, [0127]) and to “mitigate the problem of dark spots” (Yamazaki, [0011]). Regarding dependent claim 11, Hotta, as previously modified by Yamazaki, Miyamoto, and Li, teaches the display device according to claim 10. However, as previously combined, they do not teach wherein each of the plurality of light-emitting elements is an organic electroluminescence element. However, Yamazaki further teaches wherein each of the plurality of light-emitting elements is an organic electroluminescence element (Fig. 1, 309; [0127], “The organic light emitting element 309 is formed on the third inorganic insulation layer 116.”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display device as described by the combination of Hotta, Yamazaki, Miyamoto, and Li with the organic light emitting element of Yamazaki so as to make a device with a “wider-angled field of view” (Yamazaki, [0004]). Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hotta (US 20050237441 A1), in further view of Yamazaki (US 20030089991 A1), Miyamoto (US 20200185527 A1), Li (US 20190189779 A1), and Le (US 20200227568 A1). Regarding dependent claim 3, Hotta, as previously modified by Yamazaki, Miyamoto, and Li, teaches the display device according to claim 1. However, as previously combined, they do not teach wherein the thick film electrode portion is formed of the first metal film, and the thin film electrode portion is formed of the second metal film and is provided to cover both end portions of the thick film electrode portion in a channel length direction. However, in the same field of endeavor, Le teaches wherein the thick film electrode portion is formed of the first metal film, and the thin film electrode portion is formed of the second metal film and is provided to cover both end portions of the thick film electrode portion in a channel length direction (Fig. 1, 105, 107; [0036], “A gate dielectric layer 107 may be above the gate electrode 105.”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display device as described by the combination of Hotta, Yamazaki, Miyamoto, and Li with the electrode portion layout of Le so as to have “improved performance at scaled dimensions” (Le, [0013]). Claim(s) 4 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hotta (US 20050237441 A1), in further view of Yamazaki (US 20030089991 A1), Miyamoto (US 20200185527 A1), Li (US 20190189779 A1), and Wong (US 20090026523 A1). Regarding dependent claim 4, Hotta, as previously modified by Yamazaki, Miyamoto, and Li, teaches the display device according to claim 1. However, as previously combined, they do not teach wherein the thick film electrode portion is formed of the second metal film, and the thin film electrode portion is formed of the first metal film and is provided protruding from the thick film electrode portion toward one side in a channel length direction. However, in the same field of endeavor, Wong teaches wherein the thick film electrode portion is formed of the second metal film, and the thin film electrode portion is formed of the first metal film and is provided protruding from the thick film electrode portion toward one side in a channel length direction (Fig. 6c, 44B, 16; [0122], “Specifically, the second gate electrode 44B is divided into two portions…”, (44B is specifically called the “gate electrode” while layer 16 is called a “gate cap”. 16 protrudes out of one side of 44B)). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display device as described by the combination of Hotta, Yamazaki, Miyamoto, and Li with the electrode portion layout of Wong so that only one portion “is connected to another semiconductor device” (Wong, [0122]). Regarding dependent claim 6, Hotta, as previously modified by Yamazaki, Miyamoto, Li, and Wong, teaches the display device according to claim 4. However, as previously combined, they do not teach wherein the first metal film and the second metal film are made of materials different from each other. However, Miyamoto further teaches wherein the first metal film and the second metal film are made of materials different from each other ([0048], “The first metal film 15 is an electrically conductive film made of a metal material (such as Mo, Ti, Al, Cr, or Au)…”, [0054], “The second metal film 19 is an electrically conductive film made of metal material (such as Mo, Ti, Al, Cr, or Au).”, (Since the specification does not say that the two films have to be made of the same material, and both list multiple different metal materials, it stands to reason that this source teaches that the two metal films could be made of different materials)). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display device as described by the combination of Hotta, Yamazaki, Miyamoto, and Li with the different materials of Miyamoto so as to “to reduce parasitic capacitance” (Miyamoto, [0005]). Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hotta (US 20050237441 A1), in further view of Yamazaki (US 20030089991 A1), Miyamoto (US 20200185527 A1), Li (US 20190189779 A1), and Jang (US 20220037420 A1). Regarding dependent claim 7, Hotta, as previously modified by Yamazaki, Miyamoto, and Li, teaches the display device according to claim 1. Yamazaki further teaches wherein the thin film transistor layer includes a fourth inorganic insulating film (Fig. 1,129; [0129], “The fourth inorganic insulation layer 129 is formed with an inorganic insulation material…”) and Miyamoto further teaches and a fourth metal film sequentially layered on the third metal film ([0056], “The planarization film 22 is interposed between the third metal film 21 and the transparent electrode film 23 to provide insulation therebetween. The transparent electrode film 23 is stacked on the upper layer-side of the planarization film 22. The transparent electrode film 23 is a type of electrically conductive film, is made of transparent electrode material such as indium zinc oxide (IZO)…”, (The electrode film is made of a metal, so it can be described as a fourth metal film)). However, as previously combined, they do not teach the first thin film transistor includes a first terminal electrode and a second terminal electrode separated from each other and formed of the fourth metal film, the first terminal electrode and the second terminal electrode being electrically connected to the first conductor region and the second conductor region, respectively, and the second thin film transistor includes a third terminal electrode and a fourth terminal electrode separated from each other and formed of the fourth metal film, the third terminal electrode and the fourth terminal electrode being electrically connected to the third conductor region and the fourth conductor region, respectively. However, in the same field of endeavor, Jang teaches the first thin film transistor includes a first terminal electrode and a second terminal electrode separated from each other and formed of the fourth metal film, the first terminal electrode and the second terminal electrode being electrically connected to the first conductor region and the second conductor region, respectively ([Fig. 8A, TE1, TE2; [0165], “The second conductive layer may include first and second transistor electrodes TE1 and TE2 of each transistor M. The first and second transistor electrodes TE1 and TE2 may be source and drain electrodes.”), and the second thin film transistor includes a third terminal electrode and a fourth terminal electrode separated from each other and formed of the fourth metal film, the third terminal electrode and the fourth terminal electrode being electrically connected to the third conductor region and the fourth conductor region, respectively ([Fig. 8A, TE1, TE2; [0165], “The second conductive layer may include first and second transistor electrodes TE1 and TE2 of each transistor M. The first and second transistor electrodes TE1 and TE2 may be source and drain electrodes.”, (While there is only one transistor here, this electrode structure as a whole can be applied to the two electrodes in Hotta, since it is the same for both in the present application)). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display device as described by the combination of Hotta, Yamazaki, Miyamoto, and Li with the terminal electrodes of Jang so as to “be source and drain electrodes” for the conductive regions (Jang, [0165]). Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hotta (US 20050237441 A1), in further view of Yamazaki (US 20030089991 A1), Miyamoto (US 20200185527 A1), Li (US 20190189779 A1), and Yamazaki (US 20200227562 A1, hereinafter Yamazaki2). Regarding dependent claim 5, Hotta, as previously modified by Yamazaki, Miyamoto, and Li, teaches the display device according to claim 1. However, as previously combined, they do not teach wherein the thick film electrode portion is formed of the second metal film, and the thin film electrode portion is formed of the first metal film and is provided protruding from the thick film electrode portion toward both sides in a channel length direction. However, in the same field of endeavor, Yamazaki2 teaches wherein the thick film electrode portion is formed of the second metal film, and the thin film electrode portion is formed of the first metal film and is provided protruding from the thick film electrode portion toward both sides in a channel length direction (Fig. 1B, 260a, 260b; [0190], “Although the conductor 260 functioning as the first gate electrode has a two-layer structure…” (In this two layer structure, the thin bottom part extends further on both sides than the thick part it surrounds, which aligns with the broadest reasonable interpretation of the present application)). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display device as described by the combination of Hotta, Yamazaki, Miyamoto, and Li with the electrode portion layout of Yamazaki2 so that the gate electrode “can be thermally stable” (Yamazaki2, [0187]). Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hotta (US 20050237441 A1), in further view of Yamazaki (US 20030089991 A1), Miyamoto (US 20200185527 A1), Li (US 20190189779 A1), and Okabe (US 20210036093 A1). Regarding dependent claim 12, Hotta, as previously modified by Yamazaki, Miyamoto, and Li, teaches the display device according to claim 10. However, as previously combined, they do not teach wherein the first thin film transistor is provided to configure a drive thin film transistor configured to control a current of each of the plurality of light-emitting elements. However, in the same field of endeavor, Okabe teaches wherein the first thin film transistor is provided to configure a drive thin film transistor configured to control a current of each of the plurality of light-emitting elements (Fig. 7, T4; [0058], “…the subpixel circuit includes…a drive transistor T4…”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display device as described by the combination of Hotta, Yamazaki, Miyamoto, and Li with the drive configuration of Okabe so as to generate “a drive current between the corresponding anode 22 and the cathode 25, and light (fluorescence) is emitted” (Okabe, [0042]). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 20200144312 A1, pertaining to a thin-film transistor with layered gate electrodes and multiple metal layers.. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY JAMES MATTABONI whose telephone number is (571)270-0766. The examiner can normally be reached Monday-Friday 9 AM - 5 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at 5712707996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TIMOTHY JAMES MATTABONI/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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Prosecution Timeline

Jun 21, 2024
Application Filed
Jun 29, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
Grant Probability
Low
PTA Risk
Based on 0 resolved cases by this examiner. Grant probability derived from career allowance rate.

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