DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 3 recites the limitation “the set of available candidate tap delays” in lines 1-2. There is insufficient antecedent basis for this limitation in the claim.
Claim 6 recites the limitation “the submatrix” in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 6 recites the limitation “the residual error signal” in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 7 recites the limitation “the matrix” in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 7 recites the limitation “the set of available candidate tap delays” in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 7 recites the limitation “the submatrix” in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 16 is directed to “A computer program” which is a non-statutory subject matter. “A computer program” does not fall within at least one of the four categories of patent eligible subject matter.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 12, 14, 16, 18 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Bai (US 2012/0119831 A1) in view of Wild et al. (US 2016/0087769 A1).
Consider claims 1, 14 and 16:
Bai discloses a method for operating a digital pre-distorter, DPD, for a non-linear electronic device (see Figs. 1-2 and paragraph 0021, where Bai describes a digital predistortion system 100), the method comprising:
receiving an input signal destined to be input to the non-linear electronic device (see Figs. 1-2 and paragraph 0022, where Bai describes that the digital predistortion system 100 includes a pre-distorter 110 which receives an input signal x(n) to be amplified by a power amplifier 120 which is operated in a non-linear range);
selecting, for basis functions that represent input-output characteristics of the non-linear electronic device (see Figs. 1-2 and paragraph 0024, where Bai describes a distortion modeling circuit 130 which models the non-linear characteristics of the power amplifier 120 based on the power amplifier’s input signal z(n) and output signal y(n); see Fig. 7 and paragraph 0039, where Bai describes that the model includes k basis functions), a set of tap delays (see Fig. 7 and paragraph 0039, where Bai describes that each basis function has a tapped delay line with Q tap delays),
obtaining an output signal by subjecting the input signal to a linearization function defined by the basis functions with the selected set of tap delays (see Figs. 1-2 and paragraphs 0023-0024, where Bai describes that the pre-distorter 110 generates a pre-distorted signal z(n) based on applying the basis functions and the tap delays to the input signal x(n)); and
providing the output signal as input to the non-linear electronic device (see Figs. 1-2 and paragraphs 0023-0024, where Bai describes that the pre-distorted signal z(n) is provided to the power amplifier 120).
As discussed above, Bai discloses: a set of tap delays (see Fig. 7 and paragraph 0039). However, Bai does not specifically disclose: the set of tap delays is selected using a block orthogonal matching pursuit algorithm.
Wild teaches: a set of tap delays is selected using a block orthogonal matching pursuit algorithm (see paragraph 0083, where Wild describes a search algorithm such as Orthogonal Matching Pursuit may be applied in obtaining a block of delay taps; see paragraph 0082, where Wild describes that the block of delay taps may be TAP1, TAP2, TAP3, TAP4 and TAP5).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the set of tap delays is selected using a block orthogonal matching pursuit algorithm, as taught by Wild to modify the method of Bai in order to have a more fine granular resolution of the delay taps, as discussed by Wild (see paragraph 0083).
Consider claims 2 and 18:
Bai in view of Wild discloses the invention according to claims 1 and 14 above. Bai does not specifically disclose: the selected set of tap delays are selected from a set of available candidate tap delays.
Wild teaches: selected set of tap delays are selected from a set of available candidate tap delays (see Fig. 4 and paragraph 0085, where Wild describes identifying delay taps from a delay profile).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the selected set of tap delays are selected from a set of available candidate tap delays, as taught by Wild to modify the method of Bai in order to have a more fine granular resolution of the delay taps, as discussed by Wild (see paragraph 0083).
Consider claims 12 and 22:
Bai in view of Wild discloses the invention according to claims 1 and 14 above. Bai discloses: the non-linear electronic device is a radio transceiver device (see Figs. 1-2 and paragraph 0022, where Bai describes that the non-linear electronic device is power amplifier 120; see paragraph 0002, where Bai describes that the power amplifier is used in radio-frequency communication).
Bai does not specifically disclose: the set of tap delays is selected in conjunction with carrier set-up being requested for the radio transceiver device.
Wild teaches: a set of tap delays is selected in conjunction with carrier set-up being requested for a radio transceiver device (see paragraph 0082, where Wild describes that a set of tap delays, i.e., TAP1, TAP2, TAP3, TAP4 and TAP5, is selected for transmission channels TC2 and TC3; see paragraph 0073, where Wild describes that the transmission channels TC2 and TC3 have subcarriers)
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the set of tap delays is selected in conjunction with carrier set-up being requested for the radio transceiver device, as taught by Wild to modify the method of Bai in order to have a more fine granular resolution of the delay taps, as discussed by Wild (see paragraph 0083).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Bai (US 2012/0119831 A1) in view of Wild et al. (US 2016/0087769 A1), as applied to claim 1 above, and further in view of Yang et al. (US 2020/0235792 A1).
Consider claim 3:
Bai in view of Wild discloses the method according to claim 1 above. Bai and Wild do not specifically disclose: the set of available candidate tap delays is represented by a matrix, and wherein the selected set of tap delays represents a submatrix extracted from the matrix.
Yang teaches: a set of available candidate tap delays is represented by a matrix (see paragraph 0070, where Yang describes selecting M delay taps in matrix W2), and wherein the selected set of tap delays represents a submatrix extracted from the matrix (see paragraph 0078, where Yang describes that the matrix W2 may be partitioned into four submatrices of delay taps).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the set of available candidate tap delays is represented by a matrix, and wherein the selected set of tap delays represents a submatrix extracted from the matrix, as taught by Yang to modify the method of Bai and Wild in order to have a high resolution quantizer, as discussed by Yang (see paragraph 0078).
Claims 4, 9, 10, 19 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Bai (US 2012/0119831 A1) in view of Wild et al. (US 2016/0087769 A1), as applied to claims 1 and 14 above, and further in view of Zhang et al. (US 11,562,110 B1).
Consider claims 4 and 19:
Bai in view of Wild discloses the invention according to claims 1 and 14 above. Wild discloses using OMP algorithm to select tap delays (see paragraph 0083, where Wild describes a search algorithm such as Orthogonal Matching Pursuit may be applied in obtaining delay taps). However, Wild does not explicitly disclose: a respective subset of the set of tap delays is selected at each iteration of the block-OMP algorithm.
Zhang teaches: a respective subset of the set of tap delays is selected at each iteration of the block-OMP algorithm (see col. 9, lines 1-20, where Zhang describes that the orthogonal matching pursuit (OMP) is an iterative method).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: a respective subset of the set of tap delays is selected at each iteration of the block-OMP algorithm, as taught by Zhang to modify the method of Wild in order to solve optimization problem, as discussed by Zhang (see col. 9, lines 1-20).
Consider claims 9 and 21:
Bai in view of Wild discloses the invention according to claims 1 and 14 above. Bai and Wild do not specifically disclose: a respective run of the block-OMP algorithm is performed at each of at least two stages of a cascading structure.
Zhang teaches: a respective run of the block-OMP algorithm is performed at each of at least two stages of a cascading structure (see col. 9, lines 1-20, where Zhang describes that the orthogonal matching pursuit (OMP) is an iterative method).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: a respective run of the block-OMP algorithm is performed at each of at least two stages of a cascading structure, as taught by Zhang to modify the method of Bai and Wild in order to solve optimization problem, as discussed by Zhang (see col. 9, lines 1-20).
Consider claim 10:
Bai in view of Wild and Zhang discloses the method according to claim 9 above. Bai discloses: coefficients of the basis function and the set of tap delays are alternatingly selected at each of the at least two stages (see paragraph 0039, where Bai describes that the Q tap delays are selected after basis functions are determined).
Claims 8 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Bai (US 2012/0119831 A1) in view of Wild et al. (US 2016/0087769 A1), as applied to claims 1 and 14 above, and further in view of Kodama et al. (US 2021/0294500 A1).
Consider claims 8 and 20:
Bai in view of Wild discloses the invention according to claims 1 and 14 above. Bai and Wild do not specifically disclose: each of the tap delays corresponds to an address delay and a data delay, and wherein one of the address delay and the data delay is restricted to take a value within a predetermined range of the other of the address delay and the data delay.
Kodama teaches: each of tap delays corresponds to an address delay and a data delay, and wherein one of the address delay and the data delay is restricted to take a value within a predetermined range of the other of the address delay and the data delay (see Fig.2 and paragraph 0056, where Kodama describes a delay circuit which includes a input data delay circuit 180 and an address delay circuit 182, and a delay period of the input data delay circuit 180 may be the same as the delay period of the address delay circuit 182).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: each of the tap delays corresponds to an address delay and a data delay, and wherein one of the address delay and the data delay is restricted to take a value within a predetermined range of the other of the address delay and the data delay, as taught by Kodama to modify the method of Bai in order to improve compression performance, as discussed by Kodama (see paragraph 0014).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Bai (US 2012/0119831 A1) in view of Wild et al. (US 2016/0087769 A1) and Zhang et al. (US 11,562,110 B1), as applied to claim 9 above, and further in view of Lee (US 2018/0309599 A1).
Consider claim 11:
Bai in view of Wild and Zhang discloses the method according to claim 1 above. Bai does not specifically disclose: an error produced by running the block-OMP algorithm at stage l is propagated back as input to the block-OMP algorithm run at stage l−1.
Lee teaches: an error produced by running the block-OMP algorithm at stage l is propagated back as input to the block-OMP algorithm run at stage l−1 (see Fig. 8 and paragraphs 0094-0095, where Lee describes a block stage-wise orthogonal matching pursuit (StOMP) algorithm in which a residual vector of q-th iteration is inputted to q-1-th iteration).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: an error produced by running the block-OMP algorithm at stage l is propagated back as input to the block-OMP algorithm run at stage l−1, as taught by Lee to modify the method of Bai in order to estimate an effective channel, as discussed by Lee (see paragraph 0010).
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LIHONG YU whose telephone number is (571)270-5147. The examiner can normally be reached 10:00 am-6:00 pm EST Monday-Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hannah S. Wang can be reached at (571)272-9018. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LIHONG YU/ Primary Examiner, Art Unit 2631
Prosecution Insights