Prosecution Insights
Last updated: October 04, 2026
Application No. 18/723,152

FILTER STRUCTURES

Non-Final OA §103
Filed
Jun 21, 2024
Priority
Dec 22, 2021 — GB GB 2118847.9 +1 more
Examiner
SHERIF, FATUMA G
Art Unit
Tech Center
Assignee
Forefront Rf Ltd.
OA Round
1 (Non-Final)
58%
Grant Probability
Moderate
1-2
OA Rounds
10m
Est. Remaining
74%
With Interview

Examiner Intelligence

Grants 58% of resolved cases
58%
Career Allowance Rate
222 granted / 383 resolved
-2.0% vs TC avg
Strong +16% interview lift
Without
With
+16.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
11 currently pending
Career history
399
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
78.8%
+38.8% vs TC avg
§102
7.8%
-32.2% vs TC avg
§112
5.8%
-34.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 383 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been placed in the record. Election/Restrictions Claims 16-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/26/2026. Information Disclosure Statement The information disclosure statement (IDS) submitted on 09/16/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Klomsdorf et al (U.S. Patent Pub. # US 2014/0194074 A1) in view of Oran et al (U.S. Patent No. US 11,201,602 B1) further in view of Hahn et al (U.S. Patent Pub. # US 2017/0179916A1). Regarding claim 1, Klomsdorf et al discloses a circuit configured to provide self-interference cancellation in a radio transceiver (figure 7, a feed forward cancelation circuit 710; paragraph 0049, “… The feed forward cancelation circuit 710 can cancel transmitted signals from received signals. For example, additional transmit signal cancellation can be achieved at the transceiver 310 input by applying the feed forward cancellation circuit 710 to cancel the transmit signal coupling into a receiver of the transceiver 310.”), the circuit comprising: a first circuit element provided on a first substrate and comprising one or more inductors (figure 7, a tunable inductor 740; paragraph 0049); a second circuit element provided on a second substrate and comprising one or more capacitors (figure 7, a tunable capacitor 720,; paragraph 0049); at least one switching device provided on the second substrate, the switching device being capable of switching one or more of the inductors and the capacitors into or out of a signal path (paragraph 0049, “…“…The tunable canceller 710 can couple a "cancelling signal" from the transmit port of the circulator 412 to the receive port of the circulator 416. Capacitor 720, resistor 730 and inductor 740 can be selected to provide the amplitude and phase of the cancelling signal at the transmit frequency. The capacitor 720, resistor 730, and inductor 740 can serve to couple the transmit signal to the receive port 416 thereby affecting the amplitude of the cancelling circuit. Capacitor 720 and inductor 740 can serve to adjust the phase of the cancelling signal. Capacitor 720 can provide coupling with a negative phase and inductor 740 can provide coupling with a positive phase. By selecting the circuit values of capacitor 720, resistor 730, and inductor 740, a cancelling signal can be provided, having the same amplitude and the opposite phase of the "coupled signal" coupling out of the circulator at receive port 416 at the transmit frequency.”); and a control unit adapted to control the switching device so as to adapt a response of the signal path to perform self-interference cancellation (paragraph 0039, “…The multiband transceiver 310 can provide tuning control for tunable element”). Klomsdorf et al does not disclose the first circuit element provided on a first substrate; the second circuit element provided on a second substrate and the at least one switching device provided on the second substrate, Oran et al discloses one or more inductors are provided on a first substrate (figures 1A-1B, inductors 6a-6n on a substrate 3; column 4, lines 8-14) and one or more capacitors are provided on a second substrate (figures 1A-1B, capacitors on a second substrate 1; column 3, lines 55-58). Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to use the teachings of Oran et al in to the apparatus of Klomsdorf et al, such that one or more inductors could be provided on a first substrate and one or more capacitors could be provided on a second substrate in order to achieve high quality-factor (Q-factor), ultra-wideband performance, and/or an ability to be quickly tuned as taught by Oran et al (column 1, lines 35-38). Klomsdorf et al in view Oran et al does not disclose the least one switching device provided on the second substrate. Hahn et al discloses at capacitor and at least one switching device provided on a substrate (figure 10A, capacitor and switch; paragraph 0060) Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to use the teachings of Hahn et al in to the apparatus of Klomsdorf et al in view of Oran et al, such that the capacitor and switching device could be provided on the same substrate by design preference in order to reduce the device size. Regarding claim 2, Klomsdorf et al in view of Oran et al and Hahn et al discloses the apparatus of claim 1. Klomsdorf et al discloses wherein the second circuit element comprises the control unit (paragraphs 0039 and 0049, “… the multiband transceiver 310 can provide tuning control to adjust at least one tunable element based on operating conditions of the apparatus”). Regarding claim 3, Klomsdorf et al in view of Oran et al and Hahn et al discloses the apparatus of claim 1. Klomsdorf et al does not disclose wherein the first circuit element and the second circuit element are coupled to a circuit board such that the signal path extends from a first terminal on the circuit board to a second terminal on the circuit board and the control unit is provided on the circuit board. Oran et al disclose wherein the first circuit element and the second circuit element are coupled to a circuit board such that the signal path extends from a first terminal on the circuit board to a second terminal on the circuit board (see figure 1A, first circuit element (i.e., the inductors 6a-6n) and the second circuit element (i.e., the capacitors 5a-5n), the first circuit element and the second circuit element are coupled to a circuit board; column 4, lines 4-9 and column 4, lines 36-42) . Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to use the teachings of Oran et al in to the apparatus of Klomsdorf et al, such that the first circuit element and the second circuit element could be coupled to a circuit board such that the signal path extends from a first terminal on the circuit board to a second terminal on the circuit board in order to achieve high quality-factor (Q-factor), ultra-wideband performance, and/or an ability to be quickly tuned as taught by Oran et al (column 1, lines 35-38). Klomsdorf et al in view Oran et al silent to the control unit is provided on the circuit board. Hahn et al discloses the control unit is provided on the circuit board (figure.10A, switches on PCB; paragraphs 0060, and 0062 “…. Switches of the set of switches may be operable electronically by a tuning circuit or other suitable controller”). Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to use the teachings of Hahn et al in to the apparatus of Klomsdorf et al in view of Oran et al, such that the control unit could be provided on the circuit board in order to reduce the device size. Regarding claim 4, Klomsdorf et al in view of Oran et al and Hahn et al discloses the apparatus of claim 1. Klomsdorf et al discloses wherein the control unit is configured to compare a transmit signal with a receive signal and to control the switching device in dependence on a result of that comparison (paragraphs 0039 and 0049.) Regarding claim 5, Klomsdorf et al in view of Oran et al and Hahn et al discloses the apparatus of claim 1. As discussed above, Oran et al discloses the first circuit element ((figures 1A-1B, the inductors 6a-6n; column 4, lines 8-14). Oran et al also discloses wherein the first circuit element is an integrated passives device (column 4, lines 11-14, “… the secondary circuit board 3 includes shielded integrated inductors 6a, 6b, . . . 6n formed from patterning the board's conductive layers.”). Regarding claim 6, Klomsdorf et al in view of Oran et al and Hahn et al discloses the apparatus of claim 1. As discussed above, Oran et al discloses the first substrate ((figures 1A-1B, the substrate 3; column 4, lines 8-14). Oran et al also discloses wherein the first substrate is a dielectric substrate (column 4, lines 8-11, . “…secondary circuit board 3 includes multiple conductive layers (for instance, copper metal layers separated from one another by dielectric) from which inductive structures are formed.”) Regarding claim 7, Klomsdorf et al in view of Oran et al and Hahn et al discloses the apparatus of claim 1. * As discussed above, Oran et al discloses the second circuit element (figures 1A-1B, capacitors and substrate 1; column 3, lines 55-58). Oran et al also discloses wherein the second circuit element is a semiconductor device (column 3, lines 51-53, “… the semiconductor die 1”). Regarding claim 8, Klomsdorf et al in view of Oran et al and Hahn et al discloses the apparatus of claim 1. As discussed above, Oran et al discloses the second substrate (figures 1A-1B, a second substrate 1; column 3, lines 55-58). Oran et al also discloses wherein the second substrate is a semiconductor substrate (column 3, lines 51-53, “… the semiconductor die 1”). Regarding claim 9, Klomsdorf et al in view of Oran et al and Hahn et al discloses the apparatus of claim 1. As discussed above, Oran et al discloses the first circuit element and the second circuit element (column 3, lines 55-58 and column 4, lines 8-14). Oran et al also discloses an interconnect circuit element provided on a third substrate, the interconnect circuit element electrically interconnecting the first circuit element and the second circuit element.(figure 1A, a carrier circuit board 2; column 4, lines 4-29). Regarding claim 10, Klomsdorf et al in view of Oran et al and Hahn et al discloses the apparatus of claim 9. As discussed above, Oran et al discloses wherein the interconnect circuit element comprises termination connectors terminating the signal path, the termination connectors being located on a first major face of the interconnect circuit element, and the first circuit element is connected on a second major face of the interconnect circuit element (column 4, lines 17-29). Regarding claim 11, Klomsdorf et al in view of Oran et al and Hahn et al discloses the apparatus of claim 10. As discussed above, Oran et al discloses wherein the second circuit element is connected on the first major face of the interconnect circuit element (see figure 1A, the capacitors 5a-5n; column 3, lines 55-60). Regarding claim 12, Klomsdorf et al in view of Oran et al and Hahn et al discloses the apparatus of claim 10. As discussed above, Oran et al discloses wherein the termination connectors lie in a zone surrounding the second circuit element (column 4, lines 17-29). Regarding claim 13, Klomsdorf et al in view of Oran et al and Hahn et al discloses the apparatus of claim 1. Klomsdorf et al disclose the circuit comprising a data carrier storing in non-transient form code executable by the control unit to adapt the self-interference cancellation performance of the signal path (paragraphs 0020 and 0039). Regarding claim 14, Klomsdorf et al in view of Oran et al and Hahn et al discloses the apparatus of claim 1. Klomsdorf et al wherein the signal path is coupled so as to extend between a transmit path and a receive path (paragraph 0049). Regarding claim 15, Klomsdorf et al discloses a self-interference cancellation unit (figure 2, a primary analog self-interference canceller 120; paragraph 0027) comprising: a first circuit element provided on a first substrate and comprising one or more inductors (figure 7, a tunable inductor 740; paragraph 0049); a second circuit element provided on a second substrate and comprising one or more capacitors (figure 7, a tunable capacitor 720; paragraph 0049); at least one switching device provided on the second substrate, the switching device being capable of switching one or more of the inductors and the capacitors into or out of a signal path in response to a control signal received from a control unit so as to adapt the response of the signal path to perform self-interference cancellation (paragraph 0049, “…“…The tunable canceller 710 can couple a "cancelling signal" from the transmit port of the circulator 412 to the receive port of the circulator 416. Capacitor 720, resistor 730 and inductor 740 can be selected to provide the amplitude and phase of the cancelling signal at the transmit frequency. The capacitor 720, resistor 730, and inductor 740 can serve to couple the transmit signal to the receive port 416 thereby affecting the amplitude of the cancelling circuit. Capacitor 720 and inductor 740 can serve to adjust the phase of the cancelling signal. Capacitor 720 can provide coupling with a negative phase and inductor 740 can provide coupling with a positive phase. By selecting the circuit values of capacitor 720, resistor 730, and inductor 740, a cancelling signal can be provided, having the same amplitude and the opposite phase of the "coupled signal" coupling out of the circulator at receive port 416 at the transmit frequency.”). Klomsdorf et al does not disclose the first circuit element provided on a first substrate; the second circuit element provided on a second substrate and the at least one switching device provided on the second substrate, Oran et al discloses one or more inductors are provided on a first substrate (figures 1A-1B, inductors 6a-6n on a substrate 3; column 4, lines 8-14) and one or more capacitors are provided on a second substrate (figures 1A-1B, capacitors on a second substrate 1; column 3, lines 55-58). Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to use the teachings of Oran et al in to the apparatus of Klomsdorf et al, such that one or more inductors could be provided on a first substrate and one or more capacitors could be provided on a second substrate in order to achieve high quality-factor (Q-factor), ultra-wideband performance, and/or an ability to be quickly tuned as taught by Oran et al (column 1, lines 35-38). Klomsdorf et al in view Oran et al does not disclose the least one switching device provided on the second substrate. Hahn et al discloses at capacitor and at least one switching device provided on a substrate (figure 10A, capacitor and switch; paragraph 0060) Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to use the teachings of Hahn et al in to the apparatus of Klomsdorf et al in view of Oran et al, such that the capacitor and switching device could be provided on the same substrate by design preference in order to reduce the device size. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FATUMA G SHERIF whose telephone number is (571)270-7189. The examiner can normally be reached 10am - 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, PAN YUWEN can be reached at 571-272-7855. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FATUMA G SHERIF/ Examiner, Art Unit 2649 /YUWEN PAN/ Supervisory Patent Examiner, Art Unit 2649
Read full office action

Prosecution Timeline

Jun 21, 2024
Application Filed
Sep 25, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
58%
Grant Probability
74%
With Interview (+16.0%)
3y 1m (~10m remaining)
Median Time to Grant
Low
PTA Risk
Based on 383 resolved cases by this examiner. Grant probability derived from career allowance rate.

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