DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/08/2024 is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “single conductor” in claim 1 and the “high side switching device” in claim 9 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 4, and 13- 15 rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, as based on a disclosure which is not enabling. The disclosure does not enable one of ordinary skill in the art to practice the invention without knowing the average inductance values, specs of the connector such as width, length, spacing, etc., which are critical or essential to the practice of the invention but not included in the claim(s). See In re Mayhew, 527 F.2d 1229, 188 USPQ 356 (CCPA 1976).
The application (cf. page 3: lines 19- 26) states that in common power modules designs only one single wire bond is used for the interconnection of metal patterns and/or contacts in auxiliary paths. Further the application states that the use of a comparable small cross section of a single bond wires may enhance parasitic inductances which leads to oscillations e.g. gate signals/switching losses (cf. application page 3: lines 26-30). This technical problem is solved by using a number of parallel connectors instead of a single connector such that the properties may be adjusted to a pre-defined value (cf. application page 4: lines 5-7 and lines 16-18). The application does not disclose any design rule e.g. spacing of wires/connectors for controlling the mutual inductance, or how the aspect ratio of the wire should be altered for controlling the self-inductance. The application does furthermore not explicitly state what is meant by a "pre-defined value". It is hence impossible to distinguish if the inductance has a pre-defined value or not in the finished device. The subject matter of dependent claims 4, 14 and 15 is furthermore compared with a "single connector" or "average value of inductances of corresponding path". These paths/"single connector" are however not disclosed in the application, and may have any length, diameter etcetera. The same is true for the subject matter of independent claim 13 by the statement "defining a value by which the electromagnetic characteristic of the initial power module is to be adjusted". The application does not define this value. Therefore, the intended scope of protection of the subject matter of claims 4, 13, 14 and 15 is not clear.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 13-14 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 4, 13-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are:
claim 4 “wherein the number of parallel connectors in the connection portion comprising parallel connectors reduces an inductance of an auxiliary path at least 10 % compared to an inductance of an auxiliary path comprising a single connector of a same length and a same diameter as each of the parallel connectors.” The claim or originally filed specification does not mention what the length and diameter of the connectors.
For claim 13, “defining a value by which the inductance of the initial power module is to be adjusted” it is not clear what the value is.
For claim 14, “the number of connectors in the at least one connection portion is chosen such that the inductance of the at least one auxiliary path is reduced by at least 5 %”. how many connectors are there in this case?
For claim 15, “the number of connectors in the connection portions is chosen such that gate inductances of the auxiliary paths are adjusted to differ at most 10 % from an average value of inductances of the corresponding auxiliary paths.” What is the average value of which auxiliary path?
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 7, 9, 11, are rejected under 35 U.S.C. 103 as being unpatentable over Cottet et al. (US 20190304946 A1).
Regarding claim 1, Cottet discloses a power module comprising
at least one substrate (12), ([0055], Fig. 1)
at least one switching device (14) located on the at least one substrate (12), ([0055], Fig. 1)
at least one power path (20, 20a, 20b) for supplying power to the at least one switching device (14, thyristor, IGBT, MOSFET, semiconductor switch), ([0058], Fig. 1) and
at least one auxiliary path (36) for controlling and/or monitor the at least one switching device (14), ([0059], Fig. 1)
wherein the at least one of the auxiliary path (36) comprises at least one connection portion that comprises two or more connectors (62a) electrically connected in parallel ([0072], Fig. 1)
wherein at least one of the auxiliary paths (36) comprises a connection portion (annotated below) comprising parallel connectors (62a), (Fig. 1), (The examiner is treating the remaining limitation as optional) or a connection portion that comprises a single connectors.
wherein the power module (10) comprises switching devices (14) that are associated with auxiliary paths (36, 42)
wherein at least another one of the auxiliary paths (42) comprises a connection portion (annotated below) comprising at least one of parallel connectors (62a) or a connection portion that comprises a single connector. (Fig. 1)
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Cottet does not explicitly disclose:
wherein a number of the parallel connectors is different in auxiliary paths.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have “a number of the parallel connectors is different in auxiliary paths”, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04 so as to “provide a power semiconductor module with a low gate path inductance.” (Cottet, [0012])
Regarding claim 2, Cottet discloses the power module of claim 1, wherein the at least one connection portion (annotated above) comprises parallel connectors comprises at least three connectors (62a) that are electrically connected in parallel. ([0072], Fig. 1)
Regarding claim 3, Cottet discloses the power module of claim 1 that at least one of the connectors (6a2) is in the form of a wire bond, a ribbon or a clip. ([0072], Fig. 1)
Regarding claim 4, Cottet discloses the power module of claim 1. Cottet does not explicitly disclose:
wherein the number of parallel connectors in the connection portion comprising parallel connectors reduces an inductance of an auxiliary path at least 10 % compared to an inductance of an auxiliary path comprising a single connector of a same length and a same diameter as each of the parallel connectors.
However, implicitly disclose that the number of connectors in the connection portion is such that an inductance of the auxiliary path is reduced by at least 10% compared to an inductance of the auxiliary path with a single connector in the connection portion. This must be an immediate bonus effect of the bond wire arrangement in the prior art, as they have the same arrangement of bond wires as in the application.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the number of parallel connectors in the connection portion comprising parallel connectors reduces an inductance of an auxiliary path at least 10 % compared to an inductance of an auxiliary path comprising a single connector of a same length and a same diameter as each of the parallel connectors, since it has been held that where the general conditions (i.e. essential parts) of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 so as to “provide a power semiconductor module with a low gate path inductance.” (Cottet, [0012])
Regarding claim 5, Cottet discloses the power module of claim 1, wherein the at least one switching device (14) comprises a gate (16) to control switching, wherein the auxiliary path (36) is an electrical connection to the gate (16). ([0055], Fig. 1)
Regarding claim 7, Cottet discloses the power module of claim 1, wherein the auxiliary paths (36, 42) have a same functionality, wherein the same functionality comprises a connection to a gate (16), a source, a drain, an emitter or a collector of the at least one switching device (14). ([0055, Fig. 1)
Regarding claim 9, Cottet discloses the power module of claim 1, further comprising a low side switching device (14) and a high side switching (14) device forming a half- bridge (per [0058]), wherein the connection portion (62a) is provided in auxiliary paths (36, 42) of the high side switching device (14) and the low side switching device (14). (Fig. 1)
Regarding claim 11, Cottet discloses the power module of claim 1, wherein the connection portion (62a) interconnects separate metal patterns (36,42 note the examiner is lead to believe the auxiliary paths and metal patterns are the same element due to the applicants labeling in Fig. 1), wherein the separate metal patterns are located on the same substrate (12), (the examiner is treating the remining limitation as optional) or different substrates.
Claims 6, 8, 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Cottet et al. (US 20190304946 A1) as applied to claim 1 and further in view of Cho et al. (US 20130256859 A1).
Regarding claim 6, Cottet discloses the power module of claim 1. Cottet does not disclose wherein the switching device comprises an auxiliary terminal for monitoring the switching device, wherein the auxiliary path connects the auxiliary terminal to emitter, collector, source or drain of the switching device.
However, Cho discloses:
wherein the switching device (321) comprises an auxiliary terminal (358) for monitoring (see para. [0011] about (120)- external driver IC) the switching device (321), wherein the auxiliary path (362) connects the auxiliary terminal (358) to emitter, collector, source or drain (331/332) of the switching device (321). ([0011], [0015] Fig. 3B/3C)
It would have been obvious to one skilled in the art before the effective filing date to combine ethe teachings of Cottet and Cho for the switching device comprises an auxiliary terminal for monitoring the switching device, wherein the auxiliary path connects the auxiliary terminal to emitter, collector, source or drain of the switching device in order to ”be configured to control the operation of the CNTL FETs and SYNC FETs in the first and second half-bridge circuits to, among other things, produce the desired output voltage (Cho, [0011])
Regarding claim 8, Cottet discloses the power module of claim 1, wherein the parallel connectors (62a) of the auxiliary paths (36, 42) are connected between elements (14)
Cottet does not disclose:
that comprise at least one of a contact of the at least one switching device or a metal pattern.
However, Cho discloses:
that comprise at least one of a contact (331/332) of the at least one switching device (321) (the examiner is treating the remining limitation as optional) or a metal pattern. (Fig.1)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Cottet and Cho to have a contact of the at least one switching device in order to have “higher current density and current handling capability.” (Cho, [0023])
Regarding claim 10, Cottet discloses the power module of claim 1. Cottet does not disclose wherein at least one switching device comprises several auxiliary paths wherein at least two of the auxiliary paths comprise a connection portion with parallel connectors, wherein the number of the parallel connectors is different in the auxiliary paths, or wherein one of the auxiliary paths comprises a connection portion with parallel connectors and another one of the auxiliary paths does not comprise a connection portion with parallel connectors
However, Cho discloses:
that the switching device comprises several auxiliary paths (361,362), wherein at least two of the auxiliary paths comprise a connection portion (361/362) with parallel connectors (361, 362)
Cho does not disclose:
wherein the number of the parallel connectors is different in the auxiliary paths, or wherein one of the auxiliary paths comprises a connection portion with parallel connectors and another one of the auxiliary paths does not comprise a connection portion with parallel connectors
However, Cho does disclose:
“In the present implementation an external Driver IC is shared and controls both half-bridges through electrical connection to one or more of contacts 358 on leadframe 305 by one or more wires and/or interconnects.” Which leads the examiner to believe the number of wires is a design choice.
Therefore, It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Cottet and Cho for “the number of the parallel connectors is different in the auxiliary paths, or wherein one of the auxiliary paths comprises a connection portion with parallel connectors and another one of the auxiliary paths does not comprise a connection portion with parallel connectors” in order to have “higher current density and current handling capability.” (Cho, [0023])
Regarding claim 12, Cottet discloses the power module of claim 1. Cottet does not disclose wherein at least one among the at least one switching devices comprises a contact, wherein the connection portion interconnects the contact and a metal pattern.
However, Cho discloses:
wherein at least one among the at least one switching devices (321) comprises a contact (331/332), wherein the connection portion (361/362) interconnects the contact (331/332) and a metal pattern (358). (Fig. 3C)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Cottet and Cho to have at least one among the at least one switching devices comprises a contact, wherein the connection portion interconnects the contact and a metal pattern in order to have “higher current density and current handling capability.” (Cho, [0023])
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Cottet et al. (US 20190304946 A1) in view of Mari Curbelo et al. (US 20220240376 A1).
Regarding claim 13, Cottet discloses that a method for manufacturing a power module, comprising the steps of
the initial power module (10 before connecting the wires) comprising at least one substrate (12), at least one switching device (14) located on the at least one substrate (12), at least one power path to supply power to the at least one switching device (14) and at least one auxiliary path (36) to control and/or monitor the at least one switching device (14) wherein the initial power module (10 before connecting wires) comprises at least one connection portion (annotated above in claim 1).
manufacturing a power module (10) in which the connection portion (annotated above in claim 1) comprises two or more connectors (62a) electrically connected in parallel (per [0072]). (Fig. 1)
Cottet does not disclose
specifying an electromagnetic characteristic of an initial power module, wherein the electromagnetic characteristic is an inductance of at least one auxiliary path
defining a value by which the inductance of the initial power module is to be adjusted
wherein the number of connectors is chosen such that the electromagnetic characteristic is adjusted by the defined value in respect to the initial power module.
However, Mari Curbelo discloses:
“[0036] Each of the series of conductive traces may have similar and/or the same electrical properties within the determined non-zero threshold that in one example may within five percent (5%). In other example, the electronical properties such as inductance, impedance, resistance, or the like, between each series of conductive traces may be in a range of from about 5% to about 10% or may be in a range that is greater than about 10%.” And
In [0039], “ The widths of the series of conductive traces may adjust the electrical properties (e.g., inductance, impedance) of the series of conductive traces from the first input interface to corresponding terminals at each of the power modules, to be similar and/or substantially the same if balancing is required, or to be a determined value in general with respect to each other within the determined non-zero threshold, such as five percent.”
Therefore, it would have been obvious to one skilled in the art before the effective filing date to combine teachings of Cottet and Mari Curbelo to arrive at the claimed invention with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990) so as to reduce “current imbalance in the terminal. By reducing current imbalance, a more efficient operation may be achieved.” (Nari Cubelo, [0029])
Regarding claim 14, Cottet discloses the method of claim 13. Cottet does not explicitly disclose:
wherein the number of connectors in the at least one connection portion is chosen such that the inductance of the at least one auxiliary path is reduced by at least 5 %.
However, Cottet implicitly discloses that the number of connectors in the at least one connection portion is chosen such that an inductance of the at least one auxiliary path is reduced by at least 5 %, as well as the number of connectors in the connection portions is chosen such that gate inductances of the corresponding auxiliary paths are adjusted to differ at most 10 % from an average value of the inductances of the corresponding auxiliary paths. This must be an immediate bonus effect of the bond wire arrangement in the prior art, as they have the same arrangement of bondwires as in the application.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the number of connectors in the at least one connection portion is chosen such that the inductance of the at least one auxiliary path is reduced by at least 5 %, since it has been held that where the general conditions (i.e. essential parts) of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 so as to “provide a power semiconductor module with a low gate path inductance.” (Cottet, [0012])
Regarding claim 15, Cottet discloses the method of claim 13. Cottet does not explicitly disclose wherein the power module comprises the at least one switching device that each comprises auxiliary paths, wherein the number of connectors in the connection portions is chosen such that gate inductances of the auxiliary paths are adjusted to differ at most 10 % from an average value of inductances of the corresponding auxiliary paths.
However, Cottet implicitly discloses that the number of connectors in the at least one connection portion is chosen such that an inductance of the at least one auxiliary path is reduced by at least 5 %, as well as the number of connectors in the connection portions is chosen such that gate inductances of the corresponding auxiliary paths are adjusted to differ at most 10 % from an average value of the inductances of the corresponding auxiliary paths. This must be an immediate bonus effect of the bond wire arrangement in the prior art, as they have the same arrangement of bondwires as in the application.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have wherein the number of connectors in the connection portions is chosen such that gate inductances of the auxiliary paths are adjusted to differ at most 10 % from an average value of inductances of the corresponding auxiliary paths since it has been held that where the general conditions (i.e. essential parts) of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 so as to “provide a power semiconductor module with a low gate path inductance.” (Cottet, [0012])
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Onodera et al. (US 20220320049 A1) discloses in [0007], “the voltage between the control terminal and the detection terminal is applied to the control electrode as a control voltage. The time at which the control voltage is applied to the control electrode is determined in accordance with the sum of the inductance value of the first conductive path extending from the control electrode to the control terminal and the inductance value of the second conductive path extending from the second drive electrode to the detection terminal. The inductance value of the first conductive path is mainly determined by the length of the first conductive path. The inductance value of the second conductive path is mainly determined by the length of the second conductive path. Hence, when the difference between the power semiconductor elements in the sum of the length of the first conductive path and the length of the second conductive path is reduced, variations in the sum of the inductance values will be reduced between the power semiconductor elements” and therefore, could be relied upon at a later time.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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