DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-7 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. Pub. No. US 20160149000 A1 to Sazawa et al. (herainfter “Sazawa”) in view of U.S. Pat. Pub. No. US 20110124146 A1 to Pitera et al. (hereinafter “Pitera”).
Regarding claim 1, Sazawa teaches a compound semiconductor substrate comprising:
a base layer (buffering layer 104; fig. 1) [0026] having an in-plane lattice constant of a (lattice constant of AlN) [0028];
a stress relaxation layer (lower super lattice LSL 110; fig. 1) [0039] that relaxes strain (at interfaces of layers including defects) [0040]-[0041] that is received from the base layer (104) [0040]-[0041]; and
a functional layer (device base layer 142; fig. 1) [0048] having an in-plane lattice constant of b (lattice constant of GaN) [0048] (a≠b; 104 comprising a AlN material {likely a close-packed hexagonal wurtzite crystal structure}, and 142 comprising a GaN material {also likely comprising a wurtzite crystal structure}),
wherein the base layer (104), the stress relaxation layer (110) and the functional layer (142) are disposed in order (sequentially) of the base layer (104), the stress relaxation layer (110) and the functional layer (142),
in the functional layer (142), a region where a lattice (lattice of 142) is relaxed from a crystal lattice (lattice of 110) of the base layer (110) is dominant (lower layers carrying out stress relaxation, thus allowing 142 to be “dominant”) [0040]-[0041], and
The Office asserts that AlN likely has a close-packed hexagonal wurtzite crystal structure. Support for this assertion is found at Baik, Y., and Robin AL Drew. "Aluminum nitride: processing and applications." Key Engineering Materials 122 (1996): 553 (see p. 554).
The Office asserts that GaN likely comprises a wurtzite crystal structure. Support for this assertion is found at Miwa, K., and A. Fukumoto. "First-principles calculation of the structural, electronic, and vibrational properties of gallium nitride and aluminum nitride." Physical Review B 48.11 (1993): 7897 (see table II).
Sazawa does not teach a threading dislocation density of the functional layer is lower than 2.0×109 cm−2.
Pitera, however, teaches a compound semiconductor substrate (fig. 1) with a threading dislocation density of the functional layer (140) is lower than 2.0×109 cm−2 (layer 140 comprising a dislocation density one or two orders of magnitude greater than layer 130, resulting in a dislocation density of at most 109 cm−2) [0060] & [0071].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the functional layer of Sazawa to comprise a threading dislocation density satisfying the limitations of claim 1 to allow for the increase in efficiency while also keeping the layer thin as taught by Pitera [0071].
Regarding claim 2, Sazawa in view of Pitera teaches the compound semiconductor substrate according to claim 1, wherein an in-plane lattice constant of the stress relaxation layer (110) is c that satisfies (a+c−2×b)/(2×b)≤±0.5%.
To further clarify, Sazawa teaches that 110 is a laminated structure comprising layers 112 and 114 [0030]-[0031]. Layers 112 and 114 comprise defined composition ranges [0030]-[0031], each of the compositions inherently resulting in a in-plane lattice constant as a material property i.e., the materials are crystalline and therefore have lattice constants. In other words, Sazawa establishes a finite number of identified, predictable solutions, and teaches that warpage in the substrate can be avoided even with a high amount of dopants through the embodiments of the laminated structure 110 (i.e., a reasonable expectation of success it taught; see ¶ [0029]). Claim 2 is thus rejected as comprising subject matter which would be “obvious to try” in view of Sazawa. M.P.E.P. 2143 I.
Regarding claim 3, Sazawa in view of Pitera teaches the compound semiconductor substrate according to claim 1, wherein the stress relaxation layer (110) is a laminate structure (comprising layers 112 and 114; fig. 1) [0030]-[0031], and the stress relaxation layer (110) has a first crystal layer (112; fig. 1) [0030] that is positioned in contact with a base layer side (vertically bottom side; fig. 1) [0030] and has an in-plane lattice constant of c1 that is between a and b and a second crystal layer (114; fig. 1) [0030] that is positioned in contact with a functional layer side (vertically top side) of the first crystal layer (112) and has an in-plane lattice constant of c2 that satisfies (c1+c2−2×b)/(2×b)≤±0.5%.
To further clarify, Sazawa teaches that 110 is a laminated structure comprising layers 112 and 114 [0030]-[0031]. Layers 112 and 114 comprise defined composition ranges [0030]-[0031], each of the compositions inherently resulting in a in-plane lattice constant as a material property i.e., the materials are crystalline and therefore have lattice constants. In other words, Sazawa establishes a finite number of identified, predictable solutions, and teaches that warpage in the substrate can be avoided even with a high amount of dopants through the embodiments of the laminated structure 110 (i.e., a reasonable expectation of success it taught; see ¶ [0029]). Claim 3 is thus rejected as comprising subject matter which would be “obvious to try” in view of Sazawa. M.P.E.P. 2143 I.
Regarding claim 4, Sazawa in view of Pitera teaches the compound semiconductor substrate according to claim 3, wherein the first crystal layer (112) in the stress relaxation layer (110) has a thickness of 6 nm or more and 125 nm or less [0031].
Regarding claim 5, Sazawa in view of Pitera teaches the compound semiconductor substrate according to claim 3, wherein the second crystal layer (114) in the stress relaxation layer (110) has a thickness of 6 nm or more and 125 nm or less [0031].
Regarding claim 6, Sazawa in view of Pitera teaches the compound semiconductor substrate according to claim 3, wherein the stress relaxation layer has two or more periods [0032] as a repetition count of lamination composed of the first crystal layer (112) and the second crystal layer (114), and the stress relaxation layer has (110) a thickness of 500 nm or more and 10000 nm or less [0030]-[0031].
To further clarify, Sazawa teaches a thickness of 1-10 nm for layer 112 and 15-25 nm for layer 114; see ¶¶ [0030]-[0031]. Sazawa further teaches a n/m ratio (n being the number of 112 layers and m the number of 114 layer) of 75/75 [0058]. Because {1*75 = 75} and {15*75=1125}, the thickness of 110 is 1200nm, thus reading on the claim.
Regarding claim 7, Sazawa in view of Pitera teaches the compound semiconductor substrate according to claim 3, wherein, in the stress relaxation layer, the first crystal layer (112) has a chemical composition of AlxGa1-xN (0<x≤1.0), the second crystal layer (114) has a chemical composition of AlyGa1-yN (0≤y<1.0) [0030].
Sazawa does not specifically teach that y<x is satisfied.
However, Sazawa teaches that 110 is a laminated structure comprising layers 112 and 114 [0030]-[0031]. Layers 112 and 114 comprise defined composition ranges [0030]-[0031], each of the compositions inherently resulting in a in-plane lattice constant as a material property i.e., the materials are crystalline and therefore have lattice constants. In other words, Sazawa establishes a finite number of identified, predictable solutions, and teaches that warpage in the substrate can be avoided even with a high amount of dopants through the embodiments of the laminated structure 110 (i.e., a reasonable expectation of success it taught; see ¶ [0029]). Claim 3 is thus rejected as comprising subject matter which would be “obvious to try” in view of Sazawa. M.P.E.P. 2143 I.
Regarding claim 12, Sazawa in view of Pitera teaches the compound semiconductor substrate according to claim 1, further comprising: an active layer (144; fig. 1) [0036] that is positioned on the functional layer (142) and has an in-plane lattice constant (lattice constant of material in [0048]) that pseudomorphically matches (compare Al0.2Ga0.8N and GaN) [0048] and the in-plane lattice constant b of the functional layer (144).
Claims 10 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Sazawa in view of Pitera as applied to claims 1 and 3 above, and further in view of Japanese Pat. Pub. No. JP 2020077831 A, which is of record, to Sato et al. (hereinafter “Sato”).
Regarding claim 10, Sazawa in view of Pitera does not teach the compound semiconductor substrate according to claim 3, wherein the functional layer has a lattice relaxation ratio of 60% or higher with respect to the base layer.
Sato, however, teaches a compound semiconductor substrate (fig. 1) wherein the functional layer (31; fig. 1) [0028] has a lattice relaxation ratio of 60% or higher [0028] with respect to the base layer [0028].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the substrate of Sazawa to comprise a functional layer which has a stress relaxation rate of 60% or higher to suppress three-dimensional growth as taught by Sato [0028].
Regarding claim 13, Sazawa in view of Pitera teaches the compound semiconductor substrate according to claim 1, further comprising: an active layer (144; fig. 1) [0036] that is positioned on the functional layer (142) and has an in-plane lattice constant (lattice constant of material in [0048]) that pseudomorphically matches (compare Al0.2Ga0.8N and GaN) [0048] and the in-plane lattice constant b of the functional layer (144).
Sazawa in view of Pitera does not teach a contact layer that is positioned on the active layer.
Sato, however, teaches a compound semiconductor substrate (fig. 1) wherein a contact layer (electrode 14; fig. 1) [0055] is positioned on the active layer (light emitting section 35; fig. 1) [0056].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the substrate of Sazawa to comprise a contact layer on the active layer to inject electrons into the active layer as taught by Sato [0053].
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Sazawa in view of Pitera as applied to claim 3 above, and further in view of US 20200287354 A1 to Sato et al. (hereinafter “Sato 354”).
Regarding claim 11, Sazawa in view of Pitera does not teach the compound semiconductor substrate according to claim 3, further comprising: an interlayer that is positioned in contact with the base layer between the base layer and the stress relaxation layer.
Sato 354, however, teaches a compound semiconductor substrate including an interlayer (layer 30; fig. 1) [0029] that is positioned in contact with the base layer (11; fig. 1) [0021] between the base layer (11) and the stress relaxation layer (unit 35; fig. 1) [0031].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the substrate of Sazawa to comprise an interlayer satisfying the limitations of claim 11 to prevent cracks during formation as taught by Sato 354 [0029].
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Sazawa in view of Pitera as applied to claim 1 above, and further in view of U.S. Pat. Pub. No. US 20170236906 A1 to Yamada et al. (hereinafter “Yamada”).
Regarding claim 16, Sazawa teaches the compound semiconductor substrate according to claim 1, wherein a surface of the compound semiconductor substrate is a mirror surface.
Yamada, however, teaches that the surface of a compound semiconductor substrate (surface of 108; fig. 1) [0060] is a mirror surface [0060].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form the surface of the compound semiconductor substrate to have a mirror surface to increase device operation as taught by Yamada [0060].
Allowable Subject Matter
Claims 8-9, 14, and 15 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 8, there is no reference which teaches “an in-plane lattice constant of c3 that satisfies (c1+c2+c3−3×b)/(3×b)≤±0.5%.” The closest art US 20130248815 A1 to Fuke et al. which teaches a compound semiconductor substrate with three super lattice structures, but does not teach the lattice constant relationship, or, teach the person of ordinary skill in the art what they need in order to arrive at this limitation through routine experimentation, render it obvious to try, etc. Claim 9 is allowable only by virtue of its dependence on claim 8.
Regarding claim 14, a reference is not found which obviates the deficiencies of Sazawa in view of Sato. In specific, Sato teaches metals for the contact layer (band gap of zero). No reference is found which would reasonably teach the changing of this material.
Regarding claim 15, no reference is found which comprises a stress relaxation layer which further reflects light generated from the active layer. Some references are found which have a separate layer to reflect light (as in Sato 354; element 34) but this layer is not part of a stress relaxation layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN EDWARD CUTLER whose telephone number is (703)756-5415. The examiner can normally be reached Monday-Friday 7:30 am - 5:00 pm Eastern Time.
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/ETHAN EDWARD CUTLER/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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