Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, and 8-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by “Panasonic” (WO2013/186966. Examiner’s note: the citations refer to the English translation of Panasonic).
Regarding claim 1, Panasonic anticipates 1. A multilayer substrate comprising: a plurality of double-sided substrates including a first metal pattern formed on one surface, a second metal pattern formed on another surface, and a metal via connecting the first and second metal patterns (Fig. 19, page 2, bottom, page 6, bottom; the insulating layers 11 are a plurality of double-sided substrates including a first copper foil pattern 12 formed on one surface, a second copper foil pattern 12 formed on another surface, and a paste via 13 connecting the first and second copper foil patterns 12);
and a first conductive paste via formed of conductive paste that connects the first metal pattern and the second metal pattern between the double-sided substrates adjacent to each other in a double-sided substrate block in which the plurality of double-sided substrates are stacked (Fig. 19, page 2, bottom, page 6, bottom; a first paste via 13 connects the first and second copper foil patterns 12 between the insulating layers 11 adjacent to each other in a double-sided substrate block in which the plurality of double-sided insulating layers 11 are stacked),
wherein a conductive path is formed from the first metal pattern in the double-sided substrate on the one side of a pair of the double-sided substrates adjacent to each other to the second metal pattern via the metal via, the second metal pattern, the first conductive paste via, the first metal pattern in a double-sided substrate on another side, and the metal via (Fig. 19, page 2, bottom, page 6, bottom; a conductive path is formed from the first copper foil pattern 12 in the double-sided insulating layer 11 on the one side of a pair of the double-sided insulating layers 11 adjacent to each other to the second copper foil pattern 12 via the paste via 13, the second metal pattern, the first conductive paste via 13, the first copper foil pattern 12 in a double-sided substrate on another side, and the paste via 13).
Regarding claim 2, Panasonic anticipates 2. The multilayer substrate according to claim 1, wherein in the double-sided substrate block, three or more of the double-sided substrates are stacked (Fig. 19, page 2, bottom, page 6, bottom; in the double-sided substrate block, three or more of the double-sided insulating layers 11 are stacked),
and a conductive path is formed from the first metal pattern furthest on the one side in the double-sided substrate block to the second metal pattern furthest on the another side in the double-sided substrate block via each of the double-sided substrates and a plurality of first conductive paste vias connecting the double-sided substrates (Fig. 19, page 2, bottom, page 6, bottom; a conductive path is formed from the first copper foil pattern 12 furthest on the one side in the double-sided substrate block to the second copper foil pattern 12 furthest on the another side in the double-sided substrate block via each of the double-sided insulating layers 11 and a plurality of first conductive paste vias 13 connecting the double-sided insulating layers 11).
Regarding claim 3, Panasonic anticipates 3. The multilayer substrate according to claim 1, further comprising a first multilayer substrate having a third metal pattern formed on one surface, a fourth metal pattern formed on another surface, a fifth metal pattern formed on an inner layer, and first non-penetrating metal vias connecting the third metal pattern and the fifth metal pattern and connecting the fifth metal pattern and the fourth metal pattern (Fig. 19, page 2, bottom, page 6, bottom; a first group of multiple insulating layers 11 have a third copper foil pattern 12 formed on one surface and a fourth copper foil pattern 12 formed on another surface, a fifth copper foil pattern 12 formed on an inner layer, and first non-penetrating paste vias 13 connecting the copper foil pattern 12 and the fifth copper foil pattern 12 and connecting the fifth copper foil pattern 12 and the fourth copper foil pattern 12),
wherein the first multilayer substrate is stacked on the double-sided substrate furthest on the one side in the double-sided substrate block (Fig. 19, page 2, bottom, page 6, bottom; the first multilayer substrate is stacked on the double-sided substrate furthest on the one side in the double-sided substrate block),
the fourth metal pattern of the first multilayer substrate and the first metal pattern furthest on the one side are connected by a second conductive paste via formed of conductive paste (Fig. 19, page 2, bottom, page 6, bottom; the fourth copper foil pattern 12 of the first multilayer substrate and the first copper foil pattern 12 furthest on the one side are connected by a second conductive paste via 13 formed of conductive paste),
and the conductive path extends from the third metal pattern to the second metal pattern furthest on the another side of the double-sided substrate block via the first non-penetrating metal via, the fifth metal pattern, the first non-penetrating metal via, the fourth metal pattern, the second conductive paste via, and the double-sided substrate block (Fig. 19, page 2, bottom, page 6, bottom; the conductive path extends from the third copper foil pattern 12 to the second copper foil pattern 12 furthest on the another side of the double-sided substrate block via the first non-penetrating paste via 13, the fifth copper foil pattern 12, the first non-penetrating paste via 13, the fourth copper foil pattern 12, the second conductive paste via 13, and the double-sided substrate block).
Regarding claim 4, Panasonic anticipates 4. The multilayer substrate according to claim 3, further comprising a second multilayer substrate having a sixth metal pattern formed on one surface, a seventh metal pattern formed on another surface, an eighth metal pattern formed on an inner layer, and second non-penetrating metal vias connecting the sixth metal pattern and the eighth metal pattern and connecting the eighth metal pattern and the seventh metal pattern (Fig. 19, page 2, bottom, page 6, bottom; a second multilayer substrate having a sixth copper foil pattern 12 formed on one surface, a seventh copper foil pattern 12 formed on another surface, an eighth copper foil pattern 12 formed on an inner layer, and second non-penetrating paste vias 13 connecting the sixth copper foil pattern 12 and the eighth copper foil pattern 12 and connecting the eighth copper foil pattern 12 and the seventh copper foil pattern 12),
wherein the second multilayer substrate is stacked on the double-sided substrate furthest on the another side in the double-sided substrate block (Fig. 19, page 2, bottom, page 6, bottom; the second multilayer substrate is stacked on the double-sided substrate furthest on the another side in the double-sided substrate block),
the sixth metal pattern of the second multilayer substrate and the second metal pattern furthest on the another side are connected by a third conductive paste via formed of conductive paste (Fig. 19, page 2, bottom, page 6, bottom; the sixth copper foil pattern 12 of the second multilayer substrate and the second metal pattern furthest on the another side are connected by a third conductive paste via 13 formed of conductive paste),
and the conductive path extends from the third metal pattern to the seventh metal pattern via the first non-penetrating metal via, the fifth metal pattern, the first non-penetrating metal via, the fourth metal pattern, the second conductive paste via, the double-sided substrate block, the third conductive paste via, the sixth metal pattern, the second non-penetrating metal via, the eighth metal pattern, and the second non-penetrating metal via (Fig. 19, page 2, bottom, page 6, bottom; the conductive path extends from the third copper foil pattern 12 to the seventh copper foil pattern 12 via the first non-penetrating paste via 13, the fifth copper foil pattern 12, the first non-penetrating paste via 13, the fourth copper foil pattern 12, the second conductive paste via 13, the double-sided substrate block, the third conductive paste via 13, the sixth copper foil pattern 12, the second non-penetrating paste via 13, the eighth copper foil pattern 12, and the second non-penetrating paste via 13).
Regarding claim 6, Panasonic anticipates 6. A multilayer substrate comprising: three or more double-sided substrates including a first metal pattern formed on one surface, a second metal pattern formed on another surface, and a metal via connecting the first and second metal patterns (Fig. 19, page 2, bottom, page 6, bottom; three or more double-sided insulating layers 11 including a first copper foil pattern 12 formed on one surface, a second copper foil pattern 12 formed on another surface, and a paste via 13 connecting the first and second copper foil pattern 12);
in a double-sided substrate block in which the three or more double-sided substrates are stacked, a first conductive paste via formed of conductive paste that connects the first metal pattern and the second metal pattern between a pair of the double-sided substrates adjacent to each other (Fig. 19, page 2, bottom, page 6, bottom; in a double-sided substrate block in which the three or more double-sided insulating layers 11 are stacked, a first conductive paste via 13 formed of conductive paste that connects the first copper foil pattern 12 and the second copper foil pattern 12 between a pair of the double-sided substrates adjacent to each other);
and a fourth conductive paste via formed of conductive paste that connects the second metal pattern of a double-sided substrate on the another side of the pair of double-sided substrates and a first metal pattern of a double-sided substrate adjacent to the another side of a double-sided substrate including the second metal pattern (Fig. 19, page 2, bottom, page 6, bottom; a fourth conductive paste via 13 formed of conductive paste that connects the second copper foil pattern 12 of a double-sided substrate on the another side of the pair of double-sided substrates and a first copper foil pattern 12 of a double-sided substrate adjacent to the another side of a double-sided substrate including the second copper foil pattern 12).
Regarding claim 8, Panasonic anticipates 8. The multilayer substrate according to claim 2, further comprising a first multilayer substrate having a third metal pattern formed on one surface, a fourth metal pattern formed on another surface, a fifth metal pattern formed on an inner layer, and first non-penetrating metal vias connecting the third metal pattern and the fifth metal pattern and connecting the fifth metal pattern and the fourth metal pattern (Fig. 19, page 2, bottom, page 6, bottom; a first multilayer substrate having a third copper foil pattern 12 formed on one surface, a fourth copper foil pattern 12 formed on another surface, a fifth copper foil pattern 12 formed on an inner layer, and first non-penetrating paste vias 13 connecting the third copper foil pattern 12 and the fifth copper foil pattern 12 and connecting the fifth copper foil pattern 12 and the fourth copper foil pattern 12),
wherein the first multilayer substrate is stacked on the double-sided substrate furthest on the one side in the double-sided substrate block (Fig. 19, page 2, bottom, page 6, bottom; the first multilayer substrate is stacked on the double-sided substrate furthest on the one side in the double-sided substrate block),
the fourth metal pattern of the first multilayer substrate and the first metal pattern furthest on the one side are connected by a second conductive paste via formed of conductive paste (Fig. 19, page 2, bottom, page 6, bottom; the fourth copper foil pattern 12 of the first multilayer substrate and the first copper foil pattern 12 furthest on the one side are connected by a second conductive paste via 13 formed of conductive paste),
and the conductive path extends from the third metal pattern to the second metal pattern furthest on the another side of the double-sided substrate block via the first non-penetrating metal via, the fifth metal pattern, the first non-penetrating metal via, the fourth metal pattern, the second conductive paste via, and the double-sided substrate block (Fig. 19, page 2, bottom, page 6, bottom; the conductive path extends from the third copper foil pattern 12 to the second copper foil pattern 12 furthest on the another side of the double-sided substrate block via the first non-penetrating paste via 13, the fifth copper foil pattern 12, the first non-penetrating paste via 13, the fourth copper foil pattern 12, the second conductive paste via 13, and the double-sided substrate block).
Regarding claim 9, Panasonic anticipates 9. The multilayer substrate according to claim 4, further comprising a second multilayer substrate having a sixth metal pattern formed on one surface, a seventh metal pattern formed on another surface, an eighth metal pattern formed on an inner layer, and second non-penetrating metal vias connecting the sixth metal pattern and the eighth metal pattern and connecting the eighth metal pattern and the seventh metal pattern (Fig. 19, page 2, bottom, page 6, bottom; comprising a second multilayer substrate having a sixth copper foil pattern 12 formed on one surface, a seventh copper foil pattern 12 formed on another surface, an eighth copper foil pattern 12 formed on an inner layer, and second non-penetrating paste vias 13 connecting the sixth copper foil pattern 12 and the eighth copper foil pattern 12 and connecting the eighth copper foil pattern 12 and the seventh copper foil pattern 12),
wherein the second multilayer substrate is stacked on the double-sided substrate furthest on the another side in the double-sided substrate block (Fig. 19, page 2, bottom, page 6, bottom; the second multilayer substrate is stacked on the double-sided substrate furthest on the another side in the double-sided substrate block),
the sixth metal pattern of the second multilayer substrate and the second metal pattern furthest on the another side are connected by a third conductive paste via formed of conductive paste (Fig. 19, page 2, bottom, page 6, bottom; the sixth copper foil pattern 12of the second multilayer substrate and the second copper foil pattern 12furthest on the another side are connected by a third conductive paste via 13 formed of conductive paste),
and the conductive path extends from the third metal pattern to the seventh metal pattern via the first non-penetrating metal via, the fifth metal pattern, the first non-penetrating metal via, the fourth metal pattern, the second conductive paste via, the double-sided substrate block, the third conductive paste via, the sixth metal pattern, the second non-penetrating metal via, the eighth metal pattern, and the second non-penetrating metal via (Fig. 19, page 2, bottom, page 6, bottom; the conductive path extends from the third copper foil pattern 12 to the seventh copper foil pattern 12 via the first non-penetrating paste via 13, the fifth copper foil pattern 12, the first non-penetrating paste via 13, the fourth copper foil pattern 12, the second conductive paste via 13, the double-sided substrate block, the third conductive paste via 13, the sixth copper foil pattern 12, the second non-penetrating paste via 13, the eighth copper foil pattern 12, and the second non-penetrating paste via 13).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 5 and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable Panasonic in view of “Sato” (US 2018/0019198).
Regarding claim 5, Panasonic discloses the claimed invention as applied to claim 1, above.
Panasonic does not disclose the limitations of claim 5.
Sato discloses 5. The multilayer substrate according to claim 1, the multilayer substrate being a pitch conversion module that includes a plurality of the conductive paths insulated from each other (Fig. 1, [0032], [0037]; the interposer 100 being a pitch conversion module that includes a plurality of the conductive paths insulated from each other),
wherein an interval between the second metal patterns furthest on the another side in each of the conductive paths is wider than an interval between the first metal patterns furthest on the one side in each of the conductive paths (Fig. 1, [0032], [0037]; the wiring L1 and connection terminals C2 on the top side of the interposer has a smaller interval than the interval between the metal patterns on the opposite or bottom side of the interposer).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Panasonic’s multilayer substrate with Sato’s pitch conversion module in order to be capable of corresponding to a variety of pitch conversions and being inexpensive as compared to the one in the related art, as suggested by Sato at Abstract.
Regarding claim 10, Panasonic discloses the claimed invention as applied to claim 2, above.
Panasonic does not disclose the limitations of claim 10.
Sato discloses 10. The multilayer substrate according to claim 2, the multilayer substrate being a pitch conversion module that includes a plurality of the conductive paths insulated from each other (Fig. 1, [0032], [0037]; the interposer 100 being a pitch conversion module that includes a plurality of the conductive paths insulated from each other),
wherein an interval between the second metal patterns furthest on the another side in each of the conductive paths is wider than an interval between the first metal patterns furthest on the one side in each of the conductive paths (Fig. 1, [0032], [0037]; the wiring L1 and connection terminals C2 on the top side of the interposer has a smaller interval than the interval between the metal patterns on the opposite or bottom side of the interposer).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Panasonic’s multilayer substrate with Sato’s pitch conversion module in order to be capable of corresponding to a variety of pitch conversions and being inexpensive as compared to the one in the related art, as suggested by Sato at Abstract.
Regarding claim 11, Panasonic discloses the claimed invention as applied to claim 3, above.
Panasonic does not disclose the limitations of claim 11.
Sato discloses 11. The multilayer substrate according to claim 3, the multilayer substrate being a pitch conversion module that includes a plurality of the conductive paths insulated from each other (Fig. 1, [0032], [0037]; the interposer 100 being a pitch conversion module that includes a plurality of the conductive paths insulated from each other),
wherein an interval between the second metal patterns furthest on the another side in each of the conductive paths is wider than an interval between the first metal patterns furthest on the one side in each of the conductive paths (Fig. 1, [0032], [0037]; the wiring L1 and connection terminals C2 on the top side of the interposer has a smaller interval than the interval between the metal patterns on the opposite or bottom side of the interposer).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Panasonic’s multilayer substrate with Sato’s pitch conversion module in order to be capable of corresponding to a variety of pitch conversions and being inexpensive as compared to the one in the related art, as suggested by Sato at Abstract.
Regarding claim 12, Panasonic discloses the claimed invention as applied to claim 4, above.
Panasonic does not disclose the limitations of claim 12.
Sato discloses 12. The multilayer substrate according to claim 4, the multilayer substrate being a pitch conversion module that includes a plurality of the conductive paths insulated from each other (Fig. 1, [0032], [0037]; the interposer 100 being a pitch conversion module that includes a plurality of the conductive paths insulated from each other),
wherein an interval between the second metal patterns furthest on the another side in each of the conductive paths is wider than an interval between the first metal patterns furthest on the one side in each of the conductive paths (Fig. 1, [0032], [0037]; the wiring L1 and connection terminals C2 on the top side of the interposer has a smaller interval than the interval between the metal patterns on the opposite or bottom side of the interposer).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Panasonic’s multilayer substrate with Sato’s pitch conversion module in order to be capable of corresponding to a variety of pitch conversions and being inexpensive as compared to the one in the related art, as suggested by Sato at Abstract.
Claims 7 and 13 are rejected under 35 U.S.C. 103 as being unpatentable Panasonic in view of “Nagata” (US 10,712,383).
Regarding claim 7, Panasonic discloses the claimed invention as applied to claim 1, above.
Panasonic discloses the multilayer substrate according to claim 1 (Fig. 19, page 2, bottom, page 6, bottom; the insulating layers 11).
Panasonic does not disclose A jig comprising: a contact that can come into contact with an inspection object to perform electrical inspection, wherein the contact and the multilayer substrate are electrically connected.
Nagata discloses 7. A jig comprising: a contact that can come into contact with an inspection object to perform electrical inspection, wherein the contact and the multilayer substrate are electrically connected (Fig. 1, col. 2, line 35, col. 3, line 45; the inspection jig 1 comprises probes 42 and the contactor 40 which is a multilayer substrate that are electrically connected).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Panasonic’s multilayer substrate with Nagata’s inspection jig in order to provide an inspection jig capable of suppressing breakdown of contact portions of a flexible substrate, as suggested by Nagata at col. 1, lines 32-35.
Regarding claim 13, Panasonic discloses a multilayer substrate comprising: three or more double-sided substrates including a first metal pattern formed on one surface, a second metal pattern formed on another surface, and a metal via connecting the first and second metal patterns (Fig. 19, page 2, bottom, page 6, bottom; three or more double-sided insulating layers 11 including a first copper foil pattern 12 formed on one surface, a second copper foil pattern 12 formed on another surface, and a paste via 13 connecting the first and second copper foil pattern 12);
in a double-sided substrate block in which the three or more double-sided substrates are stacked, a first conductive paste via formed of conductive paste that connects the first metal pattern and the second metal pattern between a pair of the double-sided substrates adjacent to each other (Fig. 19, page 2, bottom, page 6, bottom; in a double-sided substrate block in which the three or more double-sided insulating layers 11 are stacked, a first conductive paste via 13 formed of conductive paste that connects the first copper foil pattern 12 and the second copper foil pattern 12 between a pair of the double-sided substrates adjacent to each other);
and a fourth conductive paste via formed of conductive paste that connects the second metal pattern of a double-sided substrate on the another side of the pair of double-sided substrates and a first metal pattern of a double-sided substrate adjacent to the another side of a double-sided substrate including the second metal pattern (Fig. 19, page 2, bottom, page 6, bottom; a fourth conductive paste via 13 formed of conductive paste that connects the second copper foil pattern 12 of a double-sided substrate on the another side of the pair of double-sided substrates and a first copper foil pattern 12 of a double-sided substrate adjacent to the another side of a double-sided substrate including the second copper foil pattern 12).
Panasonic does not disclose 13. A jig comprising: a contact capable of contacting an inspection object to perform electrical inspection, wherein the contact and the multilayer substrate are electrically connected.
Nagata discloses 13. A jig comprising: a contact capable of contacting an inspection object to perform electrical inspection, wherein the contact and the multilayer substrate are electrically connected (Fig. 1, col. 2, line 35, col. 3, line 45; the inspection jig 1 comprises probes 42 and the contactor 40 which is a multilayer substrate that are electrically connected).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Panasonic’s multilayer substrate with Nagata’s inspection jig in order to provide an inspection jig capable of suppressing breakdown of contact portions of a flexible substrate, as suggested by Nagata at col. 1, lines 32-35.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Imayoshi, US 2017/0018492, discloses a pitch conversion module.
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/STANLEY TSO/Primary Examiner, Art Unit 2847