Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, 6-7 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Tanabe et al. [US Patent 6403475] in view of Tanabe et al. [US PGPUB 20030143864] (hereinafter Tanabe and Tanabe864).
Regarding claim 1, Tanabe teaches a preparation method for a solar cell, comprising steps of:
providing a silicon wafer (1, Col. 7, lines 60-62) having a first surface and a second surface opposite to the first surface (Fig. 1);
forming an ultrathin silicon oxide layer (5 or 16, Col. 8, lines 1-4 or Col. 11, lines 57-58; ultrathin in view of the thicknesses of the layers deposited) on the first surface of the silicon wafer (Fig. 1/12), and sequentially forming a phosphorus-doped amorphous silicon layer (not shown, Col 14, lines 4-6) and a silicon oxide (41, Col. 14, line 8) mask layer (Fig. 18/19, wherein silicon oxide layer 41 is structural capable of being referred to as a mask because in step of Fig. 19, the silicon oxide layer 41 prevents the formation of material 43 on region of surface of layers beneath it) on the ultrathin silicon oxide layer (Fig. 18/19, Col 13, lines 57-67/ Col 14, lines 1-10); and
annealing the silicon wafer to convert the phosphorus-doped amorphous silicon layer into a phosphorus-doped polycrystalline silicon layer (Col. 14, lines 11-23).
Tanabe does not specifically disclose annealing the silicon wafer to densify the silicon oxide mask layer.
However, a person having ordinary skills in the art will find it at least obvious, if not inherent that the silicon oxide mask layer 41 in Tanabe’s device will be densified at least based on the rationale that the process of the claim is disclosed by Tanabe. In other words, there is no other limitation that is claimed to suggest that the silicon oxide mask layer 41 of Tanabe would not densify due to the annealing process.
Referring to the invention of Tanabe864, Tanabe864 teaches annealing the silicon wafer to densify a silicon oxide layer (Para 155).
In view of such teaching by Tanabe864, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Tanabe comprise the teachings of Tanabe864 in order to improve the quality of the silicon oxide material.
Regarding claim 6, Tanabe teaches a preparation method wherein a thickness of the phosphorus-doped amorphous silicon layer is from 30 nm to 300 nm (Col. 14, lines 1-7).
Regarding claim 7, Tanabe teaches a preparation method wherein a thickness of the phosphorus-doped amorphous silicon layer is from about 50 nm.
The modified invention does not specifically disclose that the phosphorus-doped amorphous silicon layer is from 100 nm to 150 nm.
However, it is noted that Tanabe discloses that the polycrystalline silicon film 43 has a coarse surface and a large surface area, making it possible to increase the amount of electric charge stored in the capacitor element for storing data (Col. 14, lines 11-23).
In view of such teaching by Tanabe, a person having ordinary skills in the art would find it at least obvious to alter or manipulate the physical and chemical characteristics of the phosphorus-doped amorphous silicon layer 43 in order to achieve increase the amount of electric charge stored in the device. Thus, as well known in the art, the thickness (among other alteration/manipulations that can be done) of the phosphorus-doped amorphous silicon layer could be increased to achieve optimal charge. Such a rationale at least based on relying on teachings, suggestions, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention (MPEP 2143.I.G).
Thus, a person having ordinary skills in the art, would have at least found it obvious to determine the optimum thickness of the polycrystalline silicon film to increase electric charge (see MPEP 2144.05).
Regarding claim 11, Tanabe teaches a preparation method wherein the silicon wafer is a P-type silicon wafer (Col. 7, lines 60-61).
Regarding claim 12, Tanabe teaches a preparation method wherein after the annealing the silicon wafer, the preparation method further comprises:
patterning the silicon oxide mask layer on the first surface to remove a part of the silicon oxide mask layer to form a patterned region (Fig. 22, at least in view of through hole 51).
In view of another interpretation of Tanabe et al. [US Patent 6403475], claim 1 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Tanabe et al. [US Patent 6403475] in view of Tanabe et al. [US PGPUB 20030143864] (hereinafter Tanabe475 and Tanabe864).
Regarding claim 1, Tanabe475 teaches a preparation method for a solar cell, comprising steps of:
providing a silicon wafer (1, Col. 7, lines 60-62) having a first surface and a second surface opposite to the first surface (Fig. 1);
forming an ultrathin silicon oxide layer (5 or 16, Col. 8, lines 1-4 or Col. 11, lines 57-58; ultrathin in view of the thicknesses of the layers deposited) on the first surface of the silicon wafer (Fig. 1/12), and sequentially forming a phosphorus-doped amorphous silicon layer (not shown, Col 14, lines 4-6) and a silicon oxide (20, Col. 13, lines 41-42) mask layer (Fig. 14/15, wherein silicon oxide layer 20 is structural capable of being referred to as a mask because in step of Fig. 14/15, the silicon oxide layer 20 prevents the formation of material 25/27 on region of surface of layers beneath it) on the ultrathin silicon oxide layer (Fig. 18/19, Col 13, lines 57-67/ Col 14, lines 1-10); and
annealing the silicon wafer to convert the phosphorus-doped amorphous silicon layer into a phosphorus-doped polycrystalline silicon layer (Col. 14, lines 11-23).
Tanabe475 does not specifically disclose annealing the silicon wafer to densify the silicon oxide mask layer.
However, a person having ordinary skills in the art will find it at least obvious, if not inherent that the silicon oxide mask layer 20 in Tanabe’s device will be densified at least based on the rationale that the process of the claim is disclosed by Tanabe475. In other words, there is no other limitation that is claimed to suggest that the silicon oxide mask layer 20 of Tanabe475 would not densify due to the annealing process.
Referring to the invention of Tanabe864, Tanabe864 teaches annealing the silicon wafer to densify a silicon oxide layer (Para 155).
In view of such teaching by Tanabe864, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Tanabe475 comprise the teachings of Tanabe864 in order to improve the quality of the silicon oxide material.
Regarding claim 8, Tanabe475 teaches a preparation method, wherein a thickness of the silicon oxide mask layer is about from10 nm to 100 nm (Col. 12, lines 52-53).
Regarding claim 9, Tanabe475 teaches a preparation method, wherein a thickness of the silicon oxide mask layer is from 20 nm to 50 nm (Col. 12, lines 52-53).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Tanabe in view of Tanabe864 and further in view of Sreekala et al. [US PGPUB 20160260602] (hereinafter Sreekala).
Regarding claim 2, Tanabe teaches a preparation method wherein the phosphorus-doped amorphous silicon layer and the silicon oxide mask layer are sequentially formed on the ultrathin silicon oxide layer by chemical vapor deposition (Col. 13, line 56-57/Col. 14 lines 5-7).
The modified invention of Tanabe does not specifically disclose that the chemical vapor deposition plasma-enhanced chemical vapor deposition.
Referring to the invention of Sreekala, Sreekala discloses depositing silicon oxide and amorphous silicon via plasma-enhanced chemical vapor deposition (Para 8).
In view of such teaching by Sreekala, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the modified invention of Tanabe comprise the teachings of Sreekala at least based on the rationale of using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C) –wherein PECVD is known to allow for low deposition temperatures, good conformity, among others benefits.
Regarding claim 3 the modified invention of Tanabe specifically in view of Sreekala teaches a preparation method wherein during forming the phosphorus-doped amorphous silicon layer and the silicon oxide mask layer by the plasma- enhanced chemical vapor deposition, a deposition temperature is from 500°C to 650°C (Para 8).
Sreekala does not specifically disclose a deposition temperature of 350°C to 550°C.
However, it should be noted that it has been held that a prima facie case of obviousness exists.in the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art. It should also be noted that it is not inventive to discover the optimum or workable ranges by routine experimentation (MPEP 2144.05).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Tanabe in view of Tanabe864 and further in view of Takahashi et al. [US PGPUB 20140030879] (hereinafter Takahashi).
Regarding claim 4, the modified invention of Tanabe teaches the limitation of claim 1 upon which is depends.
The modified invention does not specifically disclose a preparation method wherein in the annealing, an annealing temperature is from 800°C to 950°C, and an annealing time is from 30 min to 120 min.
Referring to the invention of Takahashi, Takahashi teaches crystalizing amorphous silicon at a temperature of 850°C for 30 mins (Para 29).
In view of such teaching by Takahashi, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the modified invention comprise the teachings of Takahashi at least based on the rationale of using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C).
Regarding claim 5, the modified invention specifcally in view of Takahashi teaches a preparation method wherein an annealing temperature in the annealing is from 850°C to 900°C (Para 29).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Tanabe in view of Tanabe864 and further in view of Okada et al. [US PGPUB 20050126629] (hereinafter Okada).
Regarding claim 21, the modified invention of Tanabe teaches the limitation of claim 1 upon which is depends.
The modified invention does not specifically disclose a solar cell, wherein the solar cell is prepared by the preparation method of any one of claims 1.
However, it is noted Tanabe discloses that layer 43 which is a phosphorus-doped polycrystalline silicon layer is used in forming a capacitor C (Fig. 21).
Referring to the invention of Okada, Okada discloses a solar cell that also functions as a capacitor or a secondary cell and is capable of providing a stable electrical power using the solar cell (Para 11).
In view of such teaching by Okada, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the modified invention comprise the teaching of Okada, wherein the capacitor as disclosed by Tanabe is a/functions as a solar cell, thus being a backup source of power in the device.
Allowable Subject Matter
Claims 10 and 13-19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/ISMAIL A MUSE/ Primary Examiner, Art Unit 2812
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