DETAILED ACTION
This Office Action is in response to a Non-Final office action, filed on 06/19/2026, on an application filed on 06/19/2024. Claims 1-3, 7-10, 16-18, and 20 are presented for examination consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Remarks & Claim Amendments
Applicant’s Amended Claims & Arguments/Remarks filed on 06/19/2026 with respect to the 102 rejection of independent claims 1 and 10 have been fully considered but it is not persuasive.
In addressing the arguments, the references of We is still anticipated on the amended limitations in claims 1 and 10. Applicants basis of argument is “the metal layers 222 and 224 relied upon by the Office Action are not disclosed as redistribution layers of the redistribution portion 204. Rather, they are metal layers of the base
portion 202. The reference itself therefore does not support treating metal layers 222 and 224 as the claimed redistribution layers of the claimed redistribution structure”. However, the “base portion 202” is mapped to be Applicant’s “redistribution structure 202” limitation in the Examiner’s mapping. Then Accordingly, the Examiner mapped “metal layers 222 and 224” to be Applicant’s “redistribution layers 222 & 224” limitation. The reference of We DOES NOT have to say that the “metal layers 222 and 224” are layers in the “distribution layers”, since “We does not disclose the claimed subject matter described as required by the claims”. Though, the intent of the application invention, as outline in the disclosure, maybe not be aligned to the reference of We, the corresponding mapping of limitation structures of independent claims 1 and 10 to We is a proper in the rejection.
Consequently, the “claims are not to be read in a vacuum, and limitations therein are to be interpreted in light of the specification, giving the claim limitations their broadest reasonable interpretation”, in accordance to MPEP § 2111, and NOT to import the claim limitations FROM the specification, according to MPEP § 2111.01 II. The arguments presented by the Applicant’s Argument is FROM the Applicant’s Specification and NOT the scope of the structural limitations in claims 1 and 10. Therefore, the arguments that the Applicant presented are based on wanting the structures and intent of the specification and the Figures to be read into the claim limitations instead of reading the claims in light of the specification and the claimed structure, which is impermissible.
In addition, the arguments presented by the Applicant alleging that the discovery outlined in claims 1 and 10 are patentable EVEN if the remedy is allegedly obvious, is inconsequential, since the rejection was not made under the obviousness of 35 U.S.C. § 103 but under the anticipation of 35 U.S.C. § 102. The anticipation of 35 U.S.C. § 102 will not result in a patentable invention since the reference of We is an anticipatory reference disclosing every limitation recited in the claims. See MPEP § 2131.05.
Nevertheless, Applicant's Amendment and Remarks with respect to the rejection of the claims are moot in view of the new ground(s) of rejection due to the extensive amended limitations in independent claims 1 and 10.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 3, 7, 8, 9, 16, 17, 18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by We et al. (US20160163628A1 and We hereinafter).
Regarding claim 1, We discloses a packaging structure (items 202, 204, 200 of Figs. 2-3 & item 202 of Figs. 4-5 and ¶[0057-0058_0060 & 0065-0070] shows and indicates packaging structure 202_204 {structure formed by base portion 202 and redistribution portion 204, where FIG. 3 illustrates a close up view of a portion of the integrated device package 200 of FIG. 2, where integrated device package 200 includes the base portion 202 and the redistribution portion 204}), comprising: a substrate having a plurality of first conductive layers and a plurality of second conductive layers, wherein the first conductive layers and the second conductive layers have different electric property types, and the electric property types comprise a first electric property type and a second electric property type (items 240, 270, 221, 223 of Fig. 2 & items 302, 322, 240, 270, 221, 223 of Fig. 3 and ¶[0058_0060-0062_0064-0065_0067 & 0069-0072] shows and indicates packaging structure 202_204 is comprised of a substrate 270_240 {substate formed by underfill 270, indicated in ¶[0067], and dielectric layers 240, indicated in ¶[0065 & 0069]} having a plurality of first conductive layers 302 {second interconnect 302, indicated in ¶[0069-0070]} and a plurality of second conductive layers 322 {second interconnect 322, indicated in ¶[0069 & 0072]}; where first conductive layers 302 and second conductive layers 322 have different electric property types {second interconnect 302 is a ground reference signal designed by the electrical connection to via 221, indicated in ¶[0061]; second interconnect 322 is a power signal designed by the electrical connection to via 223, indicated in ¶[0062]}; and where the electric property types comprise first electric property type ground and second electric property type power); a redistribution structure which is on the substrate (items 202, 222, 224 of Figs. 2-6 and ¶[0057-0058_0060-0062_0064-0066_0068_0070 & 0073-0075] shows and indicates redistribution structure 202 {base portion 202, indicated in ¶[0057-0058_0060_0065-0066_0068 & 0070]} which is on substrate 270_240) and comprises: redistribution layers comprising a first redistribution layer, a second redistribution layer, a third redistribution layer, a fourth redistribution layer and a fifth redistribution layer arranged sequentially at intervals in a stack (Figs. 2-4 and ¶[0061-0062_0064 & 0073-0075] shows and indicates where redistribution layers 222 & 224 comprise first redistribution layer 222-1st-top, second redistribution layer 224-1st-top, third redistribution layer 222-2nd-top, a fourth redistribution layer 224-2nd-top, and fifth redistribution layer 222-3rd-top arranged sequentially at intervals in a stack formation), wherein an isolation layer is disposed between adjacent redistribution layers and is configured to electrically isolate the adjacent redistribution layers (item 220 of Fig. 3 and ¶[0058-0063 & 0073-0075] shows and indicates where isolation layer 220-between-222-1st-top_224-1st-top {dielectric layer set 220 that is between first redistribution layer 222-1st-top and second redistribution layer 224-1st-top} that is disposed between adjacent first redistribution layer 222-1st-top and second redistribution layer 224-1st-top and is configured to electrically isolate the adjacent first redistribution layer 222-1st-top and second redistribution layer 224-1st-top; and where isolation layer 220-between-224-1st-top_222-2nd-top {dielectric layer set 220 that is between second redistribution layer 224-1st-top and third redistribution layer 222-2nd-top} that is disposed between adjacent second redistribution layer 224-1st-top and third redistribution layer 222-2nd-top and is configured to electrically isolate the adjacent second redistribution layer 224-1st-top and third redistribution layer 222-2nd-top; and where isolation layer 220-between-222-2nd-top_224-2nd-top {dielectric layer set 220 that is between third redistribution layer 222-2nd-top and fourth redistribution layer 224-2nd-top} that is disposed between adjacent third redistribution layer 222-2nd-top and fourth redistribution layer 224-2nd-top and is configured to electrically isolate the adjacent third redistribution layer 222-2nd-top and fourth redistribution layer 224-2nd-top; and where isolation layer 220-between-224-2nd-top_222-3rd-top {dielectric layer set 220 that is between fourth redistribution layer 224-2nd-top and fifth redistribution layer 223-3rd-top} that is disposed between adjacent fourth redistribution layer 224-2nd-top and fifth redistribution layer 222-3rd-top and is configured to electrically isolate the adjacent fourth redistribution layer 224-2nd-top and fifth redistribution layer 222-3rd-top), wherein the first redistribution layer, the third redistribution layer and the fifth redistribution layer have the first electric property type, and the second redistribution layer and the fourth redistribution layer have the second electric property type ; the first electric property type is ground property, and the second electric property type is power property (Figs. 2-4 and ¶[0061-0062_0064 & 0073-0075] shows and indicates where first redistribution layer 222-1st-top, third redistribution layer 222-2nd-top, and fifth redistribution layer 222-3rd-top have first electric property type of ground; and where and second redistribution layer 224-1st-top and fourth redistribution layer 224-2nd-top have second electric property type of power; and where first electric property type ground is ground property; and where second electric property type power is power property); and wherein the first conductive layers are electrically connected to the first redistribution layer, the third redistribution layer and the fifth redistribution layer through first conductive pillars (item 221 of Figs. 2-6 & items 302, 304, 240, 270, 221, 223 of Fig. 3 and ¶[0058_0060-0062_0064-0065_0067 & 0069-0072] shows and indicates where first conductive layers 302 are electrically connected to first redistribution layer 222-1st-top, third redistribution layer 222-2nd-top, and fifth redistribution layer 222-3rd-top through first conductive pillars 221 {via 221 processing ground signals to the first set of metal layers 222 from second interconnect 302 through third via interconnect 304}), and the second conductive layers are electrically connected to each of the second redistribution layer and the fourth redistribution layer through second conductive pillars (item 223 of Figs. 2-6 & items 322, 240, 270, 221, 223, 324 of Fig. 3 and ¶[0058_0060-0062_0064-0065_0067 & 0069-0072] shows and indicates where second conductive layers 322 are electrically connected to each of the second redistribution layer 224-1st-top and fourth redistribution layer 224-2nd-top through second conductive pillars 223 {via 223 processing power signals to the second set of metal layers 224 from second interconnect 322 through third via interconnect 324}), the first conductive pillars being electrically isolated from the second redistribution layer and the fourth redistribution layer and the second conductive pillars being electrically isolated from the first redistribution layer, the third redistribution layer and the fifth redistribution layer (Figs. 2-6 and ¶[0058_0060-0062_0064-0065_0067 & 0069-0072] shows and indicates where first conductive pillars 221 are electrically isolated from second redistribution layer 224-1st-top and fourth redistribution layer 224-2nd-top; and where and second conductive pillars 223 are electrically isolated from first redistribution layer 222-1st-top, third redistribution layer 222-2nd-top, and fifth redistribution layer 222-3rd-top); and a plurality of conductive bumps on a surface of the redistribution structure away from the substrate, wherein a conductive bump of the plurality of conductive bumps is electrically connected to the first conductive layers or the second conductive layers through the redistribution structure (item 282 of Figs. 2-3 & items 304, 324, 306, 326 of Fig. 3 and ¶[0058_0060-0062_0064 & 0069-0074] shows and indicates a plurality of conductive bumps 282_221 & 282_223 {bumps formed by pads 282 connected to vias 221 & bumps formed by pads 282 connected to vias 223} on the surface of redistribution structure 202 away from substrate 270_240; where conductive bump 282_221 of the plurality of conductive bumps 282_221 & 282_223 is electrically connected to first conductive layers 302 through redistribution structure 202 {electrical connection from second interconnect 302 through third via interconnect 304 & fourth interconnect 306 to base portion 202}; and where conductive bump 282_223 of the plurality of conductive bumps 282_221 & 282_223 is electrically connected to second conductive layers 322 through redistribution structure 202 {electrical connection from second interconnect 322 through third via interconnect 324 & fourth interconnect 326 to base portion 202}) wherein the fifth redistribution layer is a redistribution layer farthest from the substrate among the redistribution layers (Figs. 2-6 and ¶[0058_0060-0062_0064-0065_0067 & 0069-0072] shows where fifth redistribution layer 222-3rd-top is redistribution layers 222 & 224 that is the farthest from substrate 270_240 among the redistribution layers 222 & 224).
Regarding claim 2, We discloses a packaging structure, wherein the conductive bump contacts surfaces of the redistribution layers, one or more of the first conductive pillars farthest from the substrate, or one or more of the second conductive pillars farthest from the substrate (Figs. 2-3 and ¶[0057-0058_0060-0062_0064-0066_0068_0070_0073 & 0075] shows and indicates where conductive bumps 282_221 of conductive bumps 282_221 & 282_223 contacts surfaces of redistribution layers 222 where first conductive pillars 221 is farthest from substrate 270 of substrate 270_240; and where conductive bumps 282_223 of conductive bumps 282_221 & 282_223 contacts surfaces of redistribution layers 224 where second conductive pillars 223 is farthest from substrate 270 of substrate 270_240).
Regarding claim 3, We discloses a packaging structure, wherein the conductive bump contacts a surface of one or more of the first conductive pillars farthest from the substrate, or a surface of one or more of the second conductive pillars farthest from the substrate (Figs. 2-3 and ¶[0057-0058_0060-0062_0064-0066_0068_0070_0073 & 0075] shows and indicates where conductive bumps 282_221 of conductive bumps 282_221 & 282_223 contacts surfaces of first conductive pillars 221 that is farthest from substrate 270 of substrate 270_240; and where conductive bumps 282_223 of conductive bumps 282_221 & 282_223 contacts surfaces of second conductive pillars 223 that is farthest from substrate 270 of substrate 270_240).
Regarding claim 7, We discloses a packaging structure, wherein the first conductive layers and the second conductive layers are alternately arranged at intervals (Figs. 2-3 and ¶[0069-0070 & 0072] shows where first conductive layers 302 and second conductive layers 322 are alternately arranged at intervals {much like Applicant’s Fig. 6, where first conductive layers 101 & second conductive layers 102 are alternately arranged at intervals}).
Regarding claim 8, We discloses a packaging structure, wherein a ratio of a total number of the first conductive layers and the second conductive layers to a number of the conductive bumps is in a range of 1 to 4 (Figs. 2-3 and ¶[0058_0060-0062_0064 & 0069-0074] shows where the ratio of the total number of first conductive layers 302 and second conductive layers 32 to a number of conductive bumps 282_221 & 282_223 is in the range of 1).
Regarding claim 9, We discloses a packaging structure, wherein adjacent conductive bumps are equally spaced (Fig. 2 and ¶[0058_0060-0062_0064 & 0069-0074] shows where adjacent conductive bumps 282_221 & 282_223 are equally spaced).
Regarding claim 16, see the rejection of claim 8.
Regarding claim 17, see the rejection of claim 9.
Regarding claim 18, see the rejection of claim 9.
Regarding claim 20, We discloses a packaging structure, wherein the plurality of conductive bumps comprises a first conductive bump and a second conductive bump, the first conductive bump is electrically connected to the first conductive layers through the redistribution structure, and the second conductive bump is electrically connected to the second conductive layers through the redistribution structure (Figs. 2-3 and ¶[0058_0060-0062_0064 & 0069-0074] shows and indicates where the plurality of conductive bumps 282_221 & 282_223 is comprises first conductive bump 282_221 and second conductive bump 282_223; and where first conductive bump 282_221 is electrically connected to first conductive layers 302 through redistribution structure 202 {electrical connection from second interconnect 302 through third via interconnect 304 & fourth interconnect 306 to base portion 202}; and where second conductive bump 282_223 is electrically connected to second conductive layers 322 through redistribution structure 202 {electrical connection from second interconnect 322 through third via interconnect 324 & fourth interconnect 326 to base portion 202}).
Claim 10 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by We.
Regarding claim 10, We discloses an integrated circuit board (item 200 of Figs. 2-3 and [0068] shows and indicates integrated circuit board 200 {integrated device package 200}), comprising: a packaging structure (items 202, 204, 200 of Figs. 2-3 & item 202 of Figs. 4-5 and ¶[0057-0058_0060 & 0065-0070] shows and indicates packaging structure 202_204 {structure formed by base portion 202 and redistribution portion 204, where FIG. 3 illustrates a close up view of a portion of the integrated device package 200 of FIG. 2, where integrated device package 200 includes the base portion 202 and the redistribution portion 204}), comprising: a substrate having a plurality of first conductive layers and a plurality of second conductive layers, wherein the first conductive layers and the second conductive layers have different electric property types, and the electric property types comprise a first electric property type and a second electric property type (items 240, 270, 221, 223 of Fig. 2 & items 302, 322, 240, 270, 221, 223 of Fig. 3 and ¶[0058_0060-0062_0064-0065_0067 & 0069-0072] shows and indicates packaging structure 202_204 is comprised of a substrate 270_240 {substate formed by underfill 270, indicated in ¶[0067], and dielectric layers 240, indicated in ¶[0065 & 0069]} having a plurality of first conductive layers 302 {second interconnect 302, indicated in ¶[0069-0070]} and a plurality of second conductive layers 322 {second interconnect 322, indicated in ¶[0069 & 0072]}; where first conductive layers 302 and second conductive layers 322 have different electric property types {second interconnect 302 is a ground reference signal designed by the electrical connection to via 221, indicated in ¶[0061]; second interconnect 322 is a power signal designed by the electrical connection to via 223, indicated in ¶[0062]}; and where the electric property types comprise first electric property type ground and second electric property type power); a redistribution structure which is on the substrate (items 202, 222, 224 of Figs. 2-6 and ¶[0057-0058_0060-0062_0064-0066_0068_0070 & 0073-0075] shows and indicates redistribution structure 202 {base portion 202, indicated in ¶[0057-0058_0060_0065-0066_0068 & 0070]} which is on substrate 270_240) and comprises: redistribution layers comprising a first redistribution layer, a second redistribution layer, a third redistribution layer, a fourth redistribution layer and a fifth redistribution layer arranged sequentially at intervals in a stack (Figs. 2-4 and ¶[0061-0062_0064 & 0073-0075] shows and indicates where redistribution layers 222 & 224 comprise first redistribution layer 222-1st-top, second redistribution layer 224-1st-top, third redistribution layer 222-2nd-top, a fourth redistribution layer 224-2nd-top, and fifth redistribution layer 222-3rd-top arranged sequentially at intervals in a stack formation), wherein an isolation layer is disposed between adjacent redistribution layers and is configured to electrically isolate the adjacent redistribution layers (item 220 of Fig. 3 and ¶[0058-0063 & 0073-0075] shows and indicates where isolation layer 220-between-222-1st-top_224-1st-top {dielectric layer set 220 that is between first redistribution layer 222-1st-top and second redistribution layer 224-1st-top} that is disposed between adjacent first redistribution layer 222-1st-top and second redistribution layer 224-1st-top and is configured to electrically isolate the adjacent first redistribution layer 222-1st-top and second redistribution layer 224-1st-top; and where isolation layer 220-between-224-1st-top_222-2nd-top {dielectric layer set 220 that is between second redistribution layer 224-1st-top and third redistribution layer 222-2nd-top} that is disposed between adjacent second redistribution layer 224-1st-top and third redistribution layer 222-2nd-top and is configured to electrically isolate the adjacent second redistribution layer 224-1st-top and third redistribution layer 222-2nd-top; and where isolation layer 220-between-222-2nd-top_224-2nd-top {dielectric layer set 220 that is between third redistribution layer 222-2nd-top and fourth redistribution layer 224-2nd-top} that is disposed between adjacent third redistribution layer 222-2nd-top and fourth redistribution layer 224-2nd-top and is configured to electrically isolate the adjacent third redistribution layer 222-2nd-top and fourth redistribution layer 224-2nd-top; and where isolation layer 220-between-224-2nd-top_222-3rd-top {dielectric layer set 220 that is between fourth redistribution layer 224-2nd-top and fifth redistribution layer 223-3rd-top} that is disposed between adjacent fourth redistribution layer 224-2nd-top and fifth redistribution layer 222-3rd-top and is configured to electrically isolate the adjacent fourth redistribution layer 224-2nd-top and fifth redistribution layer 222-3rd-top), wherein the first redistribution layer, the third redistribution layer and the fifth redistribution layer have the first electric property type, and the second redistribution layer and the fourth redistribution layer have the second electric property type; the first electric property type is ground property, and the second electric property type is power property (Figs. 2-4 and ¶[0061-0062_0064 & 0073-0075] shows and indicates where first redistribution layer 222-1st-top, third redistribution layer 222-2nd-top, and fifth redistribution layer 222-3rd-top have first electric property type of ground; and where and second redistribution layer 224-1st-top and fourth redistribution layer 224-2nd-top have second electric property type of power; and where first electric property type ground is ground property; and where second electric property type power is power property); and wherein the first conductive layers are electrically connected to each of the first redistribution layer, the third redistribution layer and the fifth redistribution layer through first conductive pillars (item 221 of Figs. 2-6 & items 302, 240, 270, 221, 223, 304 of Fig. 3 and ¶[0058_0060-0062_0064-0065_0067 & 0069-0072] shows and indicates where first conductive layers 302 are electrically connected to first redistribution layer 222-1st-top, third redistribution layer 222-2nd-top, and fifth redistribution layer 222-3rd-top through first conductive pillars 221 {via 221 processing ground signals to the first set of metal layers 222 from second interconnect 302 through third via interconnect 304}), and the second conductive layers are electrically connected to each of the second redistribution layer and the fourth redistribution layer through second conductive pillars (item 223 of Figs. 2-6 & items 322, 240, 270, 221, 223, 324 of Fig. 3 and ¶[0058_0060-0062_0064-0065_0067 & 0069-0072] shows and indicates where second conductive layers 322 are electrically connected to each of the second redistribution layer 224-1st-top and fourth redistribution layer 224-2nd-top through second conductive pillars 223 {via 223 processing power signals to the second set of metal layers 224 from second interconnect 322 through third via interconnect 324}), the first conductive pillars being electrically isolated from the second redistribution layer and the fourth redistribution layer and the second conductive pillars being electrically isolated from the first redistribution layer, the third redistribution layer and the fifth redistribution layer (Figs. 2-6 and ¶[0058_0060-0062_0064-0065_0067 & 0069-0072] shows and indicates where first conductive pillars 221 are electrically isolated from second redistribution layer 224-1st-top and fourth redistribution layer 224-2nd-top; and where and second conductive pillars 223 are electrically isolated from first redistribution layer 222-1st-top, third redistribution layer 222-2nd-top, and fifth redistribution layer 222-3rd-top); and a plurality of conductive bumps on a surface of the redistribution structure away from the substrate, wherein a conductive bump of the plurality of conductive bumps is electrically connected to the first conductive layers or the second conductive layers through the redistribution structure (item 282 of Figs. 2-3 & items 304, 324, 306, 326 of Fig. 3 and ¶[0058_0060-0062_0064 & 0069-0074] shows and indicates a plurality of conductive bumps 282_221 & 282_223 {bumps formed by pads 282 connected to vias 221 & bumps formed by pads 282 connected to vias 223} on the surface of redistribution structure 202 away from substrate 270_240; where conductive bump 282_221 of the plurality of conductive bumps 282_221 & 282_223 is electrically connected to first conductive layers 302 through redistribution structure 202 {electrical connection from second interconnect 302 through third via interconnect 304 & fourth interconnect 306 to base portion 202}; and where conductive bump 282_223 of the plurality of conductive bumps 282_221 & 282_223 is electrically connected to second conductive layers 322 through redistribution structure 202 {electrical connection from second interconnect 322 through third via interconnect 324 & fourth interconnect 326 to base portion 202}), wherein the fifth redistribution layer is a redistribution layer farthest from the substrate among the redistribution layers (Figs. 2-6 and ¶[0058_0060-0062_0064-0065_0067 & 0069-0072] shows where fifth redistribution layer 222-3rd-top is redistribution layers 222 & 224 that is the farthest from substrate 270_240 among the redistribution layers 222 & 224).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUILLERMO J EGOAVIL whose telephone number is (571)270-1325. The examiner can normally be reached Mon-Fri 8:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GUILLERMO J EGOAVIL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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