DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Amendment filed August 14, 2026.
Claims 1 and 3-15 are pending. Claim 1 is amended. Claims 7-15 are new. Claims 1 and 5 are independent.
Continued Examination Under 37 CFR 1.114 After Final Rejection
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on August 14, 2026 has been entered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55 received on July 1, 2024.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang (U.S. 10,210,921) in view of Park et al. (U.S. 2010/0124120; hereinafter “Park”).
Regarding independent claim 1, Hwang teaches a program operation method (see Abstract) of a three-dimensional flash memory including word lines (Fig. 1: WLs) apart from each other and stacked in a vertical direction (see col. 6, ll. 65-67; col. 7, ll. 1-12 and ll. 32-43) while extending in a horizontal direction on a substrate (see col. 6, ll. 65-67; col. 7, ll. 1-12 and ll. 32-43), and vertical channel structures formed to pass through the word lines and extending in the vertical direction (see col. 6, ll. 65-67; col. 7, ll. 1-12 and ll. 32-43), each of the vertical channel structures including a vertical channel pattern extending in the vertical direction and a ferroelectric-based data storage pattern formed to cover an outer wall of the vertical channel pattern, and the data storage pattern and the vertical channel pattern constituting memory cells corresponding to the word lines (see col. 6, ll. 65-67; col. 7, ll. 1-12 and ll. 32-43), the method comprising:
adjusting a value of a program voltage to be applied to a selected word line corresponding to a target memory cell as a target of the program operation from among the word lines by applying an incremental step pulse programming (ISPP) method (see col. 8, ll. 28-52);
applying the adjusted value of the program voltage to the selected word line (see col. 8, ll. 28-52; see also Fig. 5B: Vpgm);
applying a pass voltage to each of unselected word lines except for the selected word line from among the word lines (Fig. 5B: Vpass); and
performing the program operation on the target memory cell in response to the adjusted value of the program voltage being applied to the selected word line and the pass voltage being applied to the unselected word lines (see col. 15, ll. 7-34).
However, Hwang is silent with respect to adjusting the value of the program voltage includes adjusting the value of the program voltage to be applied to the selected word line corresponding to the target memory cell as the target of the program operation from among the word lines, based on a slope in which a voltage pulse increases in the ISPP method.
Park teaches the step of adjusting the value of the program voltage includes adjusting the value of the program voltage to be applied to the selected word line corresponding to the target memory cell as the target of the program operation from among the word lines, based on an amount of change by which a voltage pulse increases or a threshold voltage window in a slope in which a voltage pulse increases in the ISPP method (see page 3, par. 0050).
Since Park and Hwang are from the same field of endeavor, the teachings described by Park would have been recognized in the pertinent art of Hwang.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Park with the teachings of Hwang for the purpose of prevent over-programming, see Park’s page 6, par. 0117.
Regarding claim 3, Hwang in combination with Park teaches the limitations with respect to claim 1.
Furthermore, Hwang teaches wherein the adjusting of the value of the program voltage includes multi-leveling the three-dimensional flash memory by adjusting the value of the program voltage to a plurality of values (see col. 7, ll. 17-31 and ll. 44-62).
Regarding claim 6, Hwang, in combination with Park, teaches the limitations with respect to claim 1.
Furthermore, Hwang teaches wherein the applying of the pass voltage includes adjusting a value of the pass voltage based on stability of a program state that the target memory cell has due to the program operation (see col. 2, ll. 32-34 and col. 15, ll. 45-47).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Hwang and Park as applied to claim 1 above, and further in view of Li et al. (U.S. 9,875,784; hereinafter “Li”).
Regarding claim 4, Hwang, in combination with Park, teaches the limitations with respect to claim 1.
Furthermore, Hwang teaches the applying of the pass voltage includes applying a pass voltage of a positive value (Fig. 9: Vpass).
However, the combination is silent with respect to when a vertical channel pattern of a selected vertical channel structure including the target memory cell is of an N type, the adjusting of the value of the program voltage includes adjusting the value of the program voltage to a positive value.
Similar to Hwang, Li teaches a program operation method of a three-dimensional memory (see cols. 4-5, ll. 65-63 and ll. 1-11).
Furthermore, Li teaches when a vertical channel pattern of a selected vertical channel structure including the target memory cell is of an N type, the adjusting of the value of the program voltage includes adjusting the value of the program voltage to a positive value (see col. 13, ll. 10-16).
Since Li, Park and Hwang are from the same field of endeavor, the teachings described by Li would have been recognized in the pertinent art of Hwang in combination with Park.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Li with the teachings of Hwang in combination with Park for the purpose of improve channel region control and reduce leakage, see Li’s col. 12, ll. 6-7.
Allowable Subject Matter
Claims 7-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 7, there is no teaching or suggestion in the prior art of record to provide the recited step of wherein adjusting the value of the program voltage includes adjusting the value of the program voltage in a region having a large threshold voltage window in the ISPP slope.
With respect to claim 8, there is no teaching or suggestion in the prior art of record to provide the recited step of wherein adjusting the value of the program voltage in a region in which the amount of change, by which a voltage pulse increase, is gradual in the ISPP slope.
Claims 5 and 9-15 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to independent claim 5, there is no teaching or suggestion in the prior art of record to provide the recited steps of when a vertical channel pattern of a selected vertical channel structure including the target memory cell is of a P type, the adjusting of the value of the program voltage includes adjusting the value of the program voltage to a negative value, and the applying of the pass voltage includes applying a pass voltage of a negative value.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claims 1, 3-4 and 6 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
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/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825
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