Prosecution Insights
Last updated: August 16, 2026
Application No. 18/726,097

SEMICONDUCTOR DEVICE AND POWER CONVERSION DEVICE

Non-Final OA §102§103§112
Filed
Jul 01, 2024
Priority
Feb 25, 2022 — JP 2022-028605 +1 more
Examiner
LEE, WOO KYUNG
Art Unit
Tech Center
Assignee
Hitachi Astemo Ltd.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
1y 0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
161 granted / 198 resolved
+21.3% vs TC avg
Strong +16% interview lift
Without
With
+15.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
37 currently pending
Career history
222
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
49.9%
+9.9% vs TC avg
§102
21.4%
-18.6% vs TC avg
§112
28.6%
-11.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 198 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 6-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 6, it is not clear how the conductor plate and the insulation sheet can be arranged on both surfaces of the plurality of semiconductor elements, recited on lines 2-3, because as shown in Figs. 2-3 of the present application, it appears that the conductor plate 430 and the insulation sheet 440 are separate and distinct components from conductor plate 431 and insulation sheet 441. Specifically, the conductor plate 430 and the insulation sheet 440 are disposed only on the upper side of the plurality of semiconductor elements, whereas conductor plate 431 and insulation sheet 441 are disposed only on the lower side of the plurality of semiconductor elements. Consistent with the drawings, Applicants originally disclosed that “the collector side of the first power semiconductor elements 155 and 156 is joined to a second conductor plate 431” (emphasis added, [0014] of the present application), therefore, this indicates that the conductor plate 431 at a lower side is a separate conductor plate from the conductor plate 430. Therefore, it remains unclear whether the recited “the conductor plate” and “the insulation sheet” refers to a single conductor plate and a single insulation sheet arranged on both surfaces of the plurality of semiconductor elements, or instead encompass separate conductor plates and separate insulation sheets disposed on the respective upper and lower surfaces. Claim 7 depends on claim 6, therefore, claim 7 is also indefinite. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1 and 3 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Masuda et al. (US 2023/0282561, foreign priority: Aug. 18, 2020 (JP); hereinafter Masuda). Regarding claim 1, Masuda discloses for a semiconductor device, comprising that a plurality of semiconductor elements (switching element 5/electrode 6/electrode 7/control electrode 8 in power semiconductor module 1, Fig. 1A, [0047]); a conductor plate (conductive layer 23/conductor with spacer function 32, Fig. 1A) to which the plurality of semiconductor elements (5/6/7/8, Fig. 1A, [0047]) are joined; an insulation sheet (insulation layer 22, Fig. 1A) which is bonded to the face of the conductor plate (top side of 23/32, Fig. 1A) on the opposite side from the side of the plurality of semiconductor elements (opposite side of 5/6/7/8, Fig. 1A); and a resin member (resin, [0045]) that seals the plurality of semiconductor elements (5/6/7/8, Fig. 1A), the insulation sheet (22, Fig. 1A), and the conductor plate (23/32, Fig. 1A), because “Space not including any component is filled with insulating resin” (emphasis added, [0045]), wherein the conductor plate (23/32, Fig. 1A) includes a plurality of element joining regions (left and right 32 regions, Fig. 1A) to which each of the plurality of semiconductor elements (5/6/7/8, Fig. 1A) is joined, and a connection region (33, Fig. 1A) provided between the plurality of element joining regions (left and right 32 regions, Fig. 1A), wherein the insulation sheet-side surface of the conductor plate in the element joining regions protrudes from the insulation sheet-side surface of the connection region, because a rectangular shape of the left and right 32 regions are protruded vertically from a rod shape of the inter-conductor wiring portion 33 (Fig. 1A) and is bonded to the insulation sheet (22, Fig. 1A), and wherein the resin member (resin, [0045]) is added between the insulation sheet (22, Fig. 1A) and the insulation sheet-side surface of the conductor plate in the connection region (top side of 33, Fig. 1A), because “Space not including any component is filled with insulating resin” (emphasis added, [0045]). Regarding claim 3, Masuda further discloses for the semiconductor device according to claim 1 that a resin filling space (white space between top surface of 33 and 22, Fig. 1A) filled with the resin member (resin, [0045]) is formed between the insulation sheet-side surface of the connection region (top side of 33, Fig. 1A) and the insulation sheet (22, Fig. 1A), and wherein the resin member (resin, [0045]) in the resin filling space (white space between top surface of 33 and 22, Fig. 1A) is connected to a resin member (lower portion of white space in 1, Fig. 1A) that seals the plurality of semiconductor elements (5/6/7/8, Fig. 1A), the insulation sheet (22, Fig. 1A), and the conductor plate (23/32, Fig. 1A). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 4 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over by Masuda et al. (US 2023/0282561, foreign priority: Aug. 18, 2020 (JP); hereinafter Masuda). Regarding claim 4, Masuda does not explicitly disclose that the thickness of the resin filling space is equal to or greater than the thickness of the insulation sheet. However, Masuda further discloses that “An absolute value of the mutual inductance is calculated on the conditions that the inter-conductor wiring portion 33 is spaced at 0.8 mm from the conductor pattern 23a, the inter-conductor wiring portion 33 has a width of 1 mm, and the inter-conductor wiring portion 33 has a thickness of 0.4 mm” (emphasis added, [0087]), and because a thickness of a resin filling space between the top surface of the inter-conductor wiring portion 33 and the conductive layer 23 would be determined by a thickness of the inter-conductor wiring portion 33, Masuda recognizes that the thickness of the resin filling space impacts the electrical properties of the power conversion device. The thickness is therefore a result-effective variable to be optimized by repeated experiments. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, a thickness of a resin filling space between the top surface of the inter-conductor wiring portion and the conductive layer as Masuda has identified the thickness as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at the thickness equal to or greater than a thickness of the insulation layer, in order to achieve the desired electrical and thermal properties of the power conversion device, as taught by Masuda. Furthermore, the applicant has not presented persuasive evidence that the claimed thickness comparison is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed thickness). Regarding claim 8, Masuda does not explicitly disclose that DC power is converted into AC power. However, Masuda further discloses the power conversion device (Title, Fig. 8, [0128]) configured to convert electrical power for operation of the three-phase AC electric motor 140 (Fig. 8), therefore, one of ordinary skill in the power electronics art would have recognized that a power conversion device can be implemented using any of several well-known power conversion, including a DC power to AC power inverter, depending upon the electrical requirements of the load. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the power conversion device to convert DC power to AC power where the electrical load requires an AC power supply, because DC-to-AC conversion is a well-known function of inverter type power conversion devices. Claims 2 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Masuda et al. (US 2023/0282561, foreign priority: Aug. 18, 2020 (JP); hereinafter Masuda) in view of Tsuyuno et al. (US 2022/0336324, Foreign priority: Sep. 18, 2019; hereinafter Tsuyuno). The teachings of Masuda are discussed in claim 1 above. Regarding claim 2, Masuda does not explicitly disclose that the insulation sheet includes a resin insulation layer, and wherein the resin insulation layer and the resin member are in close contact with each other due to penetration by a resin component. However, Tsuyuno discloses for a power converter device that the device includes a resin insulating layer 441 formed on the second conductor plate 431 (Fig. 2) and the sealing resin 360 is in close contact with the resin insulating layer 441 (Fig. 2). Also, because Applicants do not specifically claim what a resin component refers to and/or what it is made of, Tsuyuno further discloses that “in the transfer molding process, the sealing resin 360 is injected by pressurizing the surface of the sheet-shaped member 440 so that the sealing resin 360 does not flow around” ([0049]), and therefore, one of ordinary skill in the art would have recognized that the pressurized sealing resin wets and conforms to a surface of the resin insulating layer, resulting in chemical and/or physical interaction between one or more components of the sealing resin and the resin insulation layer at the interface. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the insulation layer of Masuda with the resin insulating layer disclosed by Tsuyuno, in order to effectively seal electrical elements, thereby improving thermal properties of semiconductor power conversion devices. Regarding claim 5, Masuda does not explicitly disclose that the insulation sheet includes a laminated structure of a resin insulation layer and a metal foil, and wherein the thickness of the resin filling space is equal to or greater than the thickness of the resin insulation layer. However, Tsuyuno further discloses that a sheet-shaped member 440 includes a laminated structure of the resin insulating layer 441 and the metal foil 442 (Fig. 2), and “the thickness of the resin insulating layer 441 can be set to a constant thickness of, for example, 120 μm capable of securing insulation properties” ([0034]). Tsuyuno further discloses that “By plastically deforming the metal-based heat conduction member 450 having a thickness of, for example, 120 μm interposed between the sheet-shaped member 440 and the cooling member 340, the thickness of the metal-based heat conduction member 450 is changed to absorb the warpage or step difference generated in the second conductor plate 431 and the fourth conductor plate 433. This results in remarkable improvement in heat dissipation as compared with the case where the conductor plates are brought into contact with the cooling member 340 via the insulating layer alone” (emphasis added, [0034]), therefore, Tsuyuno recognizes that a thickness of the resin insulating layer impacts the thermal management of the semiconductor device. The thickness of the resin insulating layer is therefore, a result-effective variable to be optimized by repeated experiments, as well as the thickness of resin filling space disclosed by Masuda, as discussed in claim 4 above. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, a thickness of the resin insulating layer as Tsuyuno has identified the thickness as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at the thickness equal to or less than a thickness of the resin filling space disclosed by Masuda, in order to achieve the desired thermal properties of the device, as taught by Tsuyuno. Furthermore, the applicant has not presented persuasive evidence that the claimed thickness is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed thickness). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WOO K LEE whose telephone number is (571)270-5816. The examiner can normally be reached Monday - Friday, 8:30 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAY C KIM/Primary Examiner, Art Unit 2815 /WOO K LEE/Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Jul 01, 2024
Application Filed
Jul 14, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
97%
With Interview (+15.9%)
3y 2m (~1y 0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 198 resolved cases by this examiner. Grant probability derived from career allowance rate.

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