Prosecution Insights
Last updated: July 17, 2026
Application No. 18/726,797

DISPLAY SUBSTRATE AND DISPLAY APPARATUS

Non-Final OA §102
Filed
Jul 04, 2024
Priority
Jun 20, 2022 — CN 202210699653.8 +1 more
Examiner
ULLAH, ELIAS
Art Unit
Tech Center
Assignee
BOE Technology Group Co., Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
721 granted / 850 resolved
+24.8% vs TC avg
Moderate +8% lift
Without
With
+7.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
21 currently pending
Career history
859
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
48.0%
+8.0% vs TC avg
§102
48.2%
+8.2% vs TC avg
§112
1.3%
-38.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 850 resolved cases

Office Action

§102
DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1,11-12 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ebisuno ( US 2015/0091444 A1) IDS of the record. Regarding claims 1 and 19 Ebisuno shows a display substrate ([0005] i.e. glass substrate), comprising: a base substrate ([0005]), comprising a display region (display region 10 in FIG. 2) , and a peripheral region ( display region 11) located at a periphery of the display region ( region between display 11 and 100 see FIG. 1); wherein the display region comprises a first display region ( display region 100) and a second display region ( display region 10), and the first display region at least partially surrounds the second display region; a circuit structure layer (circuit 21/20), which is located on the base substrate and comprises a plurality of pixel circuits (PIX [0072]), a plurality of initial signal lines ([0074-0076]), and at least one electrostatic conductive line ([0074-0076]), wherein the plurality of initial signal lines are electrically connected with the plurality of pixel circuits and extend along a first direction, the at least one electrostatic conductive line extends along a second direction, and the first direction intersects with the second direction; the plurality of pixel circuits are located in the first display region, and the plurality of initial signal lines are at least located in the first display region; the at least one electrostatic conductive line is electrically connected with at least two initial signal lines (see FIG. 1-2). Regarding claims 11 and 12 Ebisuno shows a display substrate ([0005] i.e. glass substrate), wherein the at least one electrostatic conductive line is located on a side of the plurality of initial signal lines away from the base substrate and the substrate of any one of wherein the at least one electrostatic conductive line is located in the peripheral region (see FIG. 1-2 and [0072-0076]). Allowable Subject Matter Claims 2-10 and 13-18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ELIAS ULLAH/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Jul 04, 2024
Application Filed
Jul 01, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12667017
LIGHT EMITTING DEVICE MODULE AND DISPLAY APPARATUS HAVING THE SAME
2y 11m to grant Granted Jun 23, 2026
Patent 12666630
SEMICONDUCTOR DEVICE
2y 10m to grant Granted Jun 23, 2026
Patent 12667025
SEMICONDUCTOR MEMORY DEVICE
2y 1m to grant Granted Jun 23, 2026
Patent 12660722
POWER MODULE PACKAGE WITH MOLDED VIA AND DUAL SIDE PRESS-FIT PIN
3y 7m to grant Granted Jun 16, 2026
Patent 12660208
STORAGE WAFER AND MANUFACTURING METHOD OF STORAGE WAFER
3y 3m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
93%
With Interview (+7.8%)
2y 4m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 850 resolved cases by this examiner. Grant probability derived from career allowance rate.

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