DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-18 are pending and examined.
Claim Objections
Claims 5, 11-16 are objected to under 37 CFR 1.75(c) as being in improper form because a multiple dependent claim cannot depend from any other multiple dependent claim. For example. See MPEP § 608.01(n). Accordingly, the claims have not been further treated on the merits.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6, 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 11,853,385 to Luo (hereafter Luo).
Regarding independent claim 1, Luo teaches a data processing method based on a memristor array, wherein the data processing comprises a matrix-vector multiplication operation in complex domain (FIG. 4B: memory array 412), the memristor array comprises a plurality of memristor units arranged in an array and is configured to be capable of performing a multiplication-addition operation, the data processing method comprises:
acquiring a plurality of first analog signals (FIG. 6A: signal a inputted to Tx 602);
setting the memristor array, and writing data of a parameter matrix corresponding to the data processing into the memristor array (FIG. 4B: data as shown in memory cells of memory array 412), wherein a matrix in the complex domain comprises a real-portion matrix (FIG. 4B: +M read coefficients in sub-array 402 and/or -M read coefficients in sub-array 404) and an imaginary-portion matrix (FIG. 4B: +M imaginary coefficients in sub-array 406 and -M imaginary coefficients in sub-array 408); the parameter matrix comprises the real-portion matrix (FIG. 4B: +M read coefficients in sub-arrays 402 and/or -M read coefficients in sub-array 404), the imaginary-portion matrix (FIG. 4B: +M imaginary coefficients in sub-array 406), and an imaginary-portion negative matrix (FIG. 4B: -M imaginary coefficients in sub-array 408) obtained based on the imaginary-portion matrix; a plurality of parameter elements in the imaginary-portion negative matrix is in one-to-one correspondence with a plurality of parameter elements in the imaginary-portion matrix, and each parameter element in the imaginary-portion negative matrix is a negative value of a corresponding parameter element in the imaginary-portion matrix; and
inputting the plurality of first analog signals into a plurality of column signal input terminals of the set memristor array (FIG. 3: corresponding to row terminals of matrix fabric 321, see 18:59-65), respectively, controlling operation of the memristor array to perform the data processing on the plurality of first analog signals, and obtaining a plurality of second analog signals after performing the data processing at a plurality of row signal output terminals of the memristor array, respectively (FIG. 3: corresponding to column terminals of matrix fabric 321, see 18:59-65).
Regarding dependent claim 6, Luo teaches wherein each of the plurality of first analog signals comprises a first real-portion analog signal and a first imaginary-portion analog signal, acquiring the plurality of first analog signals, comprises: acquiring a vector in the complex domain used for the data processing, wherein the vector in the complex domain comprises a real-portion vector (FIG. 4B: e.g. vectors obtained from equations 6 and 7 in reverse, which occurs in encoding process) and an imaginary-portion vector (FIG. 4B: e.g. vectors obtained from equations 8 and 9 in reverse, which occurs in encoding process); and encoding the real-portion vector and the imaginary-portion vector, respectively, to obtain a plurality of first real-portion analog signals and a plurality of first imaginary-portion analog signals (FIG. 6A: process of encoding occurred between Tx 602 and Rx 604).
Regarding independent claim 17, Luo teaches an electronic apparatus, comprising:
a memristor array, configured to be capable of performing a multiplication-addition operation (FIG. 4B: memory array 412);
a signal acquiring apparatus, configured to acquire a plurality of first analog signals (FIG. 6A: signal a inputted to Tx 602);
a control driving circuit, configured to execute steps of:
setting the memristor array, and writing data of a parameter matrix corresponding to the data processing into the memristor array (FIG. 4B: data as shown in memory cells of memory array 412), wherein a matrix in the complex domain comprises a real-portion matrix (FIG. 4B: +M read coefficients in sub-array 402 and/or -M read coefficients in sub-array 404) and an imaginary-portion matrix (FIG. 4B: +M imaginary coefficients in sub-array 406 and -M imaginary coefficients in sub-array 408); the parameter matrix comprises the real-portion matrix (FIG. 4B: +M read coefficients in sub-arrays 402 and/or -M read coefficients in sub-array 404), the imaginary-portion matrix (FIG. 4B: +M imaginary coefficients in sub-array 406), and an imaginary-portion negative matrix (FIG. 4B: -M imaginary coefficients in sub-array 408) obtained based on the imaginary-portion matrix; a plurality of parameter elements in the imaginary-portion negative matrix is in one-to-one correspondence with a plurality of parameter elements in the imaginary-portion matrix, and each parameter element in the imaginary-portion negative matrix is a negative value of a corresponding parameter element in the imaginary-portion matrix; and
inputting the plurality of first analog signals into a plurality of column signal input terminals of the set memristor array (FIG. 3: corresponding to row terminals of matrix fabric 321, see 18:59-65), respectively, controlling operation of the memristor array to perform the data processing on the plurality of first analog signals, and obtaining a plurality of second analog signals after performing the data processing at a plurality of row signal output terminals of the memristor array, respectively (FIG. 3: corresponding to column terminals of matrix fabric 321, see 18:59-65).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Luo.
Regarding dependent claim 10, Luo real-portion matrix +M read coefficients, imaginary-portion matrix +M imaginary coefficients and imaginary-portion negative matrix -M read coefficients. However, Luo does not explicitly teach the parameter matrix is represent as:
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However, it would have been obvious to one with ordinary skill the in art to realize that representative of a parameter matrix is a matter of design choice, which depends on the intended calculation.
Allowable Subject Matter
Claims 2-4, 7-9, 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to dependent claim 2: wherein the memristor array comprises a first sub-array, a second sub-array, a third sub-array and a fourth sub-array, setting the memristor array, and writing the data of the parameter matrix corresponding to the data processing into the memristor array, comprises: mapping a plurality of parameter elements in the real-portion matrix to the first sub-array and the fourth sub-array, respectively, in a form of the real-portion matrix, mapping the plurality of parameter elements in the imaginary-portion matrix to the third sub-array in a form of the imaginary-portion matrix, and mapping the plurality of parameter elements in the imaginary-portion negative matrix to the second sub-array in a form of the imaginary-portion negative matrix, wherein the first sub-array and the second sub-array are located in a same row in the memristor array but do not overlap with each other in a row direction, the third sub- array and the fourth sub-array are located in a same row in the memristor array but do not overlap with each other in the row direction, and the first sub-array and the third sub- array do not overlap with each other in a column direction.
With respect to dependent claim 7: wherein inputting the plurality of first analog signals into the plurality of column signal input terminals of the set memristor array, respectively, comprises: inputting the plurality of first real-portion analog signals into column signal input terminals of the first sub-array and column signal input terminals of the third sub-array, respectively; and inputting the plurality of first imaginary-portion analog signals into column signal input terminals of the second sub-array and column signal input terminals of the fourth sub-array, respectively.
With respect to dependent claim 18: wherein the memristor array comprises a first sub-array, a second sub-array, a third sub-array and a fourth sub-array, the control driving circuit, when executing setting the memristor array, and writing the data of the parameter matrix corresponding to the data processing into the memristor array, is configured to execute steps of: mapping a plurality of parameter elements in the real-portion matrix to the first sub-array and the fourth sub-array, respectively, in a form of the real-portion matrix, mapping the plurality of parameter elements in the imaginary-portion matrix to the third sub-array in a form of the imaginary-portion matrix, and mapping the plurality of parameter elements in the imaginary-portion negative matrix to the second sub-array in a form of the imaginary-portion negative matrix, wherein the first sub-array and the second sub-array are located in a same row in the memristor array but do not overlap with each other in a row direction, the third sub- array and the fourth sub-array are located in a same row in the memristor array but do not overlap with each other in the row direction, and the first sub-array and the third sub- array do not overlap with each other in a column direction.
Conclusion
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February 11, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
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