DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 8, and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamakawa, WO 2020/090403.
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Regarding claim 1, Yamakawa teaches a semiconductor device comprising:
a semiconductor substrate 11; and
a first field effect transistor 24 provided on a first principal plane side of the semiconductor substrate, wherein
the first field effect transistor includes a semiconductor region 24C in which a channel is formed,
a gate electrode 24G that covers the semiconductor region,
a gate insulating film 24I disposed between the semiconductor region and the gate electrode,
an n-type source region (“N+” doped region in figure 4A, referred to as 24A in Specification) provided in the semiconductor substrate, and
an n-type drain region (“N+” doped region in figure 4A, referred to as 24B in Specification) provided in the semiconductor substrate,
the semiconductor region includes
an upper surface (as labeled in figure above),
a first side surface located on one side of the upper surface in a gate width direction of the gate electrode (as labeled in figure above),, and
a second side surface located on the other side of the upper surface in the gate width direction (as labeled in figure above),,
the gate electrode includes a first portion 243 facing the upper surface across the gate insulating film,
a second portion 241 facing the first side surface across the gate insulating film, and
a third portion 242 facing the second side surface across the gate insulating film, and
a conductivity type of the semiconductor region is n-type (figures 4A and 4B).
Regarding claim 8, Yamakawa teaches a imaging device comprising:
a photoelectric conversion element 21 (figure 3); and
a semiconductor device 24 for reading a charge photoelectrically converted by the photoelectric conversion element, wherein
the semiconductor device includes
a semiconductor substrate 11, and
a first field effect transistor 24 provided on a first principal plane side of the semiconductor substrate,
the first field effect transistor includes a semiconductor region 24C in which a channel is formed,
a gate electrode 24G that covers the semiconductor region,
a gate insulating film 24I disposed between the semiconductor region 24C and the gate electrode,
an n-type source region (“N+” doped region in figure 4A, referred to as 24A in Specification) provided in the semiconductor substrate, and
an n-type drain region (“N+” doped region in figure 4A, referred to as 24B in Specification) provided in the semiconductor substrate,
the semiconductor region includes an
upper surface (as labeled in figure above),
a first side surface located on one side of the upper surface in a gate width direction of the gate electrode (as labeled in figure above), and
a second side surface located on the other side of the upper surface in the gate width direction (as labeled in figure above),
the gate electrode includes
a first portion 243 facing the upper surface across the gate insulating film,
a second portion 241 facing the first side surface across the gate insulating film, and
a third portion 242 facing the second side surface across the gate insulating film, and
a conductivity type of the semiconductor region is n-type (figures 4A-4B).
Regarding claim 9, Yamakawa teaches the semiconductor device includes a floating diffusion 26 configured to accumulate a charge generated by the photoelectric conversion element, and an amplification transistor 24 configured to output, to a signal line, a pixel signal at a level corresponding to the charge accumulated in the floating diffusion, and the first field effect transistor is used as the amplification transistor (Figures 2 and 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamakawa as applied to claims 1 above, and further in view of Mutoh, US Patent Application Publication 2009/0050997.
Regarding claim 2, Yamakawa teaches a p-type region provided in the semiconductor substrate and located around the first field effect transistor, wherein the p-type region 111 (figure 4B).
Yamakawa fails to teach the p-type region contains indium as a p-type impurity.
However, Mutoh teaches indium as one of several dopant material that is conventionally-used in the art to make p-type impurity regions in a semiconductor substrate (See [0129]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Mutoh with that of Yamakawa because indium is one of several dopant material that is conventionally-used in the art to make p-type impurity regions in a semiconductor substrate.
Regarding claim 3, Yamakawa teaches the p-type region includes a first p-type region located immediately below the semiconductor region (figure 4B).
Regarding claim 4, Yamakawa teaches an element isolation layer 112 provided on the first principal plane side of the semiconductor substrate and adjacent to the first field effect transistor, wherein the p-type region includes a second p-type region 21a located on an opposite side of the first field effect transistor across the element isolation layer (figure 4B).
Regarding claim 5, Yamakawa teaches a part of the second p-type region extends immediately below the element isolation layer (figure 4B).
Regarding claim 6, Yamakawa teaches a second field effect transistor 22 provided in the semiconductor substrate and having a channel formed in the second p-type region (as shown in figure 20A).
Regarding claim 7, Yamakawa fails to teach the conductivity type of the semiconductor substrate is n-type.
However, Mutoh teaches that the n-type transistor 10B is generally-formed within a n-type substrate 31 and contains a p-type well 32/33 (as shown in figure 8)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Mutoh with that of Yamakawa because it is generally-known in the art that n-type substrates are used to make n-type transistors of Yamakawa.
Conclusion
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/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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