DETAILED ACTION
National Stage Application
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.437 and PCT Rule 11.13(l) because they do not include the following reference sign(s) mentioned in the description: 21, 321, and 322. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are also objected to as failing to comply with 37 CFR 1.437 and PCT Rule 11.13(m) because:
(a) reference character “10” has been used to designate both “Photon Detector” (in Fig. 9) and “CMOS Front End” (in Fig. 1); and
(b) reference character “20” has been used to designate both “CMOS Front End” (in Fig. 9) and “Photon Detector” (in Fig. 1).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Interpretation
MPEP § 2111.01 stated that “… Under a broadest reasonable interpretation (BRI), words of the claim must be given their plain meaning, unless such meaning is inconsistent with the specification. The plain meaning of a term means the ordinary and customary meaning given to the term by those of ordinary skill in the art at the relevant time. The ordinary and customary meaning of a term may be evidenced by a variety of sources, including the words of the claims themselves, the specification, drawings, and prior art. However, the best source for determining the meaning of a claim term is the specification - the greatest clarity is obtained when the specification serves as a glossary for the claim terms …”). Thus under a broadest reasonable interpretation, the greatest clarity is obtained when the specification (e.g., see “… range detector circuit 320 is configured so that a range between the first threshold level Vlowerlimit and the second threshold level Vupperlimit is provided with a hysteresis. Upon startup, the target range is set and once the integrator output signal is within this range, the boundary is widened by a value large enough to prevent switching back due to noise. Once the integrator output signal falls outside the widened range, the boundary is set back to the target value …” in the first paragraph on pg. 29) serves as a glossary for the claim term “hysteresis”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of pre-AIA 35 U.S.C. 112, second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 10-12 is/are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 10 recites the limitation “the analog output signal” before the last line and claim 11 recites the limitation “the analog output signal” in lines 3 and 7. The antecedent basis for these limitations in the claims can be either “an analog output voltage signal” in claim 8 or “an analog output signal” in claim 10.
Claim 12 recites the limitation “the digital-to-analog converter” in line 9. The antecedent basis for these limitations in the claims can be either “a digital-to-analog converter” in claim 9 or “a second digital-to-analog converter” in claim 12.
Claim(s) dependent on the claim(s) discussed above is/are also indefinite for the same reasons.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were effectively filed absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned at the time a later invention was effectively filed in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5 and 7 is/are rejected under U.S.C. 102(a)(1) as being anticipated by Robbins (US 4,481,597).
In regard to claim 1, Robbins discloses an electric circuitry for baseline restoration, comprising:
(a) an input terminal to receive an input signal having pulses above or below a baseline level (e.g., “… differential amplifier 18 has two inputs, one of which is from the PMT 12. The other is on a conductor 20 which is a portion of a feedback loop … feedback signal carries with it the accumulated amplifier offsets for errors. This includes noise components. This also includes DC offsets in the integration system which comprises the feedback loop …” in the last column 3 paragraph and the second column 5 paragraph);
(b) a baseline sampling circuit for providing a baseline output signal representing a baseline level of the input signal (e.g., “… timing sequencer 30 forms a signal which triggers closure of the switch 26. The switch is normally held open to allow continuous integration …” in the fourth column 4 paragraph);
(c) an integrator circuit to receive an error signal representing an error of the baseline level of the input signal, the integrator circuit being configured to provide an integrator output signal being a representation of an integration of the error signal (e.g., “… integrator 22 forms an output signal for another amplifier 38. The amplifier 38 is a track and hold amplifier. The amplifier 38 forms an output signal which is input to the differential amplifier 32. Also, the amplifier 38 forms a signal which is input to a pair of comparators …” in the third column 5 paragraph);
(d) a digitization circuit to provide a digital output signal being a digital representation of the integrator output signal (e.g., “… output pulses of the comparators 40 and 42 are pulses causing a bidirectional counter 44 to count up or down. The counter has two input terminals, one for counting up and another for counting down. The two input terminals are arranged to increment or decrement the count stored in the counter 44. This count has the form of a multibit digital word. It is stored in the counter and increases or decreases depending on the last pulse received. Whatever the case, it is a digital word …” in the third column 4 paragraph); and
(e) an output stage to provide a baseline restoration output signal representing a corrected baseline level of the input signal, the output stage being configured to provide the baseline restoration output signal in dependence on the digital output signal (e.g., “… a digital word which is converted into an analog value by a digital to analog converter 48 at the output of the counter 44. The analog output of the converter 48 is input to the feedback conducter 20 and back to the differential amplifier 18 …” in the third column 4 paragraph).
In regard to claim 2 which is dependent on claim 1, Robbins also discloses that the digitization circuit comprises an analog-to-digital converter being configured to convert the integrator output signal to the digital output signal, wherein the digitization circuit is configured to hold the digital output signal for further processing by the output stage (e.g., “… amplifier 38 forms a signal which is input to a pair of comparators … output pulses of the comparators 40 and 42 are pulses causing a bidirectional counter 44 to count up or down. The counter has two input terminals, one for counting up and another for counting down. The two input terminals are arranged to increment or decrement the count stored in the counter 44. This count has the form of a multibit digital word. It is stored in the counter and increases or decreases depending on the last pulse received. Whatever the case, it is a digital word …” in the third column 4 paragraph).
In regard to claim 3 which is dependent on claim 1, Robbins also discloses that the output stage comprises a digital-to-analog converter to convert the digital output signal to the baseline restoration output signal (e.g., “… a digital word which is converted into an analog value by a digital to analog converter 48 at the output of the counter 44. The analog output of the converter 48 is input to the feedback conducter 20 and back to the differential amplifier 18 …” in the third column 4 paragraph).
In regard to claim 4 which is dependent on claim 1, Robbins also discloses that the digitization circuit comprises a counter circuit, wherein the counter circuit is configured to change a state of the counter circuit in dependence on a level of the integrator output signal, wherein the counter circuit is configured to generate the digital output signal in dependence on the state of the counter circuit (e.g., “… output pulses of the comparators 40 and 42 are pulses causing a bidirectional counter 44 to count up or down. The counter has two input terminals, one for counting up and another for counting down. The two input terminals are arranged to increment or decrement the count stored in the counter 44. This count has the form of a multibit digital word. It is stored in the counter and increases or decreases depending on the last pulse received. Whatever the case, it is a digital word …” in the third column 4 paragraph).
In regard to claim 5 which is dependent on claim 4, Robbins also discloses that the digitization circuit comprises a range detector circuit, wherein the range detector circuit is configured to evaluate the level of the integrator output signal in relation to a first and second threshold level, wherein the range detector circuit is configured to control the counter circuit in dependence on the evaluated level of the integrator output signal (e.g., “… output pulses of the comparators 40 and 42 are pulses causing a bidirectional counter 44 to count up or down. The counter has two input terminals, one for counting up and another for counting down. The two input terminals are arranged to increment or decrement the count stored in the counter 44. This count has the form of a multibit digital word. It is stored in the counter and increases or decreases depending on the last pulse received. Whatever the case, it is a digital word …” in the third column 4 paragraph).
In regard to claim 7 which is dependent on claim 5, Robbins also discloses that the range detector circuit is configured to generate a first control signal applied to the counter circuit, if the range detector circuit evaluates the level of the integrator output signal being below the first threshold level, and to generate a second control signal applied to the counter circuit, if the range detector circuit evaluates the level of the integrator output signal being above the second threshold level, wherein the counter circuit is configured to increment the state of the counter circuit, if the counter circuit receives the first control signal, wherein the counter circuit is configured to decrement the state of the counter circuit, if the counter circuit receives the second control signal (e.g., “… output pulses of the comparators 40 and 42 are pulses causing a bidirectional counter 44 to count up or down. The counter has two input terminals, one for counting up and another for counting down. The two input terminals are arranged to increment or decrement the count stored in the counter 44. This count has the form of a multibit digital word. It is stored in the counter and increases or decreases depending on the last pulse received. Whatever the case, it is a digital word …” in the third column 4 paragraph).
Claim(s) 1-4, 14, and 15 is/are rejected under U.S.C. 102(a)(2) as being anticipated by Riehl et al. (US 2023/0367025).
In regard to claim 1, Riehl et al. disclose an electric circuitry for baseline restoration, comprising:
(a) an input terminal to receive an input signal having pulses above or below a baseline level (e.g., “… Example 30 is a photon-counting computed tomography ("PCCT") system comprising … a baseline restoration ("BLR") circuit connected to the signal chain, the BLR circuit comprising an input comparator …” in paragraph 98);
(b) a baseline sampling circuit for providing a baseline output signal representing a baseline level of the input signal (e.g., “… comparator only needs to sample once per CLK pulse, the dead time can be used to implement chopper stabilization controlled by a signal φ … input comparator for comparing a voltage pulse output from the signal chain with a baseline voltage …” in paragraphs 55 and 98);
(c) an integrator circuit to receive an error signal representing an error of the baseline level of the input signal, the integrator circuit being configured to provide an integrator output signal being a representation of an integration of the error signal (e.g., “… low-pass filter acts as an integrator … conventional chopper stabilization scheme, an input signal is first inverted, then applied to an amplifier. The output of the amplifier is again inverted and passed through a low-pass filter that rejects signals at the chopper frequency. For signals applied to the amplifier, the two inversions cancel out and have no theoretical effect. But offsets in the amplifier are modulated to the chopper frequency and removed by the low-pass filter. Thus the chopper-stabilized amplifier may appear as if it has no offset … any of Examples 30-38 may further include the BLR circuit being clocked and chopper stabilization being applied to null out the offset of the input comparator …” in paragraphs 48, 57, and 107);
(d) a digitization circuit to provide a digital output signal being a digital representation of the integrator output signal (e.g., “… comparator plus one-bit DAC … input comparator outputting a single bit indicative of whether the shaper voltage is above or below the baseline voltage …” in paragraphs 46 and 98); and
(e) an output stage to provide a baseline restoration output signal representing a corrected baseline level of the input signal, the output stage being configured to provide the baseline restoration output signal in dependence on the digital output signal (e.g., “… the input comparator outputting a single bit indicative of whether the shaper voltage is above or below the baseline voltage and a low pass filter connected to filter a voltage signal output from the input comparator … PCCT system of Example 30 further including the BLR circuit further comprising a transconductor connected to receive a filtered voltage signal output from the low pass filter … and feed the current signal back to an input of the signal chain …” in paragraphs 98 and 99).
In regard to claim 2 which is dependent on claim 1, Riehl et al. also disclose that the digitization circuit comprises an analog-to-digital converter being configured to convert the integrator output signal to the digital output signal, wherein the digitization circuit is configured to hold the digital output signal for further processing by the output stage (e.g., “… comparator plus one-bit DAC … input comparator outputting a single bit indicative of whether the shaper voltage is above or below the baseline voltage …” in paragraphs 46 and 98).
In regard to claim 3 which is dependent on claim 1, Riehl et al. also disclose that the output stage comprises a digital-to-analog converter to convert the digital output signal to the baseline restoration output signal (e.g., “… digital signal POUT … is processed using an AND gate 1204 along with a clock signal CLK to produce a signal UP … causes the switch 1206 to turn on for a period of time. This in turn causes a pulse of current from the current source 1208 to be conducted to the filter capacitor 1214. The pulse of current causes the voltage FILT to increment by an amount determined by the pulse timing and value of current source 1208. Similarly, the inverse of POUT is processed using an AND gate 1207 along with CLK to produce a signal DN … causes the switch 1210 to turn on for a period of time. This in turn causes a pulse of current from the current source 1212 to be conducted to the filter capacitor 1214. The pulse of current causes the voltage FILT to decrement by an amount determined by the pulse timing and value of current source 1208 … any of Examples 30-35 may further include the BLR circuit being clocked…” in paragraphs 54 and 104).
In regard to claim 4 which is dependent on claim 1, Riehl et al. also disclose that the digitization circuit comprises a counter circuit, wherein the counter circuit is configured to change a state of the counter circuit in dependence on a level of the integrator output signal, wherein the counter circuit is configured to generate the digital output signal in dependence on the state of the counter circuit (e.g., “… comparator plus one-bit DAC … input comparator outputting a single bit indicative of whether the shaper voltage is above or below the baseline voltage …” in paragraphs 46 and 98).
In regard to claim 14, the cited prior art is applied as in claim 1 above. Riehl et al. disclose a photon counting circuitry, comprising:
(a) a photon detector having a photon sensitive area, the photon detector being configured to generate a current signal having pulses above or below a baseline, wherein the photon detector is configured to generate a respective one of the pulses, when a photon hits the photon sensitive area (e.g., “… Example 30 is a photon-counting computed tomography ("PCCT") system comprising … a photon-counting detector ("PCD") comprising a sensor for registering an interaction with an X-ray photon received at the PCD after passing through an object of interest and forwarding a pulse indicative of the interaction to a signal chain …” in paragraph 98);
(b) a front-end electronic circuitry having an input side to receive the current signal and having an output side to provide an output voltage signal in response to the current signal (e.g., “… any of Examples 30-32 may further include the signal chain comprising a charge sensing amplifier ("CSA") for amplifying the pulse received from the sensor and outputting an amplified pulse; and a pulse shaper ("PS") for shaping the amplified pulse and producing the voltage pulse output from the signal chain …” in paragraph 101);
(c) an energy discriminator being connected to the front-end electronic circuitry, the energy discriminator being configured to generate a digital signal in dependence on a comparison of a level of the output voltage signal with at least one threshold value (e.g., “… discriminators 910 quantize the current pulses according to their energy, which quantized pulses are in turn counted by the counters 912 … any of Examples 30-32 may further include a counting circuit for categorizing and counting the voltage pulse output from the signal chain …” in paragraphs 48 and 102); and
(d) the electric circuitry for baseline restoration being connected between the input side and the output side of the front-end electronic circuitry, wherein the electric circuitry for baseline restoration receives the output voltage signal provided by the front-end electronic circuitry at the input terminal as the input signal (e.g., “… BLR circuit comprising an input comparator for comparing a voltage pulse output from the signal chain … BLR circuit further comprising … feed the current signal back to an input of the signal chain …” in paragraphs 98 and 99).
In regard to claim 15, the cited prior art is applied as in claim 14 above. Riehl et al. disclose a device for medical diagnostics, comprising a photon counting circuitry, wherein the device is configured as an X-ray apparatus or a computed tomography scanner (e.g., “… Example 30 is a photon-counting computed tomography ("PCCT") system comprising an X-ray source for generating an X-ray photons; and a photon-counting detector ("PCD") comprising a sensor for registering an interaction with an X-ray photon received at the PCD after passing through an object of interest and forwarding a pulse indicative of the interaction to a signal chain; and a baseline restoration ("BLR") circuit connected to the signal chain …” in paragraph 98).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Riehl et al. (US 2023/0367025) in view of Robbins (US 4,481,597).
In regard to claim 5 which is dependent on claim 4, the circuitry of Riehl et al. lacks an explicit description of details of the “… BLR circuit …” such as a range detector circuit configured to control the counter circuit in dependence on evaluation of the integrator output signal’s level in relation to first and second threshold levels. However, “… BLR circuit …” details are known to one of ordinary skill in the art (e.g., see “… output pulses of the comparators 40 and 42 are pulses causing a bidirectional counter 44 to count up or down. The counter has two input terminals, one for counting up and another for counting down. The two input terminals are arranged to increment or decrement the count stored in the counter 44. This count has the form of a multibit digital word. It is stored in the counter and increases or decreases depending on the last pulse received. Whatever the case, it is a digital word … incremental scale factor of the feedback loop is determined in part by the count capacity of the counter 44 and the spacing of the set point voltages for the comparators 40 and 42. That, in turn, depends on the setting at the adjustable resistors 88 and 90 …” in the third column 4 paragraph and the first column 6 paragraph of Robbins). It should be noted that “when a patent claims a structure already known in the prior art that is altered by the mere substitution of one element for another known in the field, the combination must do more than yield a predictable results”. KSR International Co. v. Teleflex Inc., 550 U.S. 398 at 416, 82 USPQ2d 1385 (2007) at 1395 (citing United States v. Adams, 383 U.S. 39, 40 [148 USPQ 479] (1966)). See MPEP § 2143. In this case, one of ordinary skill in the art could have substituted a known conventional BLR circuit (e.g., comprising details such as “spacing of the set point voltages for the comparators 40 and 42”, in order to achieve a desired “incremental scale factor of the feedback loop”) for the BLR circuit of Riehl et al. and the results of the substitution would have been predictable. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a known conventional BLR circuit (e.g., comprising details such as a range detector circuit, wherein the range detector circuit is configured to evaluate the level of the integrator output signal in relation to a first and second threshold level, wherein the range detector circuit is configured to control the counter circuit in dependence on the evaluated level of the integrator output signal) as the BLR circuit of Riehl et al.
In regard to claim 7 which is dependent on claim 5, the circuitry of Riehl et al. lacks an explicit description of details of the “… BLR circuit …” such as the range detector circuit is configured to generate a first control signal applied to the counter circuit, if the range detector circuit evaluates the level of the integrator output signal being below the first threshold level, and to generate a second control signal applied to the counter circuit, if the range detector circuit evaluates the level of the integrator output signal being above the second threshold level, wherein the counter circuit is configured to increment the state of the counter circuit, if the counter circuit receives the first control signal, wherein the counter circuit is configured to decrement the state of the counter circuit, if the counter circuit receives the second control signal. However, “… BLR circuit …” details are known to one of ordinary skill in the art (e.g., see “… output pulses of the comparators 40 and 42 are pulses causing a bidirectional counter 44 to count up or down. The counter has two input terminals, one for counting up and another for counting down. The two input terminals are arranged to increment or decrement the count stored in the counter 44. This count has the form of a multibit digital word. It is stored in the counter and increases or decreases depending on the last pulse received. Whatever the case, it is a digital word … incremental scale factor of the feedback loop is determined in part by the count capacity of the counter 44 and the spacing of the set point voltages for the comparators 40 and 42. That, in turn, depends on the setting at the adjustable resistors 88 and 90 …” in the third column 4 paragraph and the first column 6 paragraph of Robbins). It should be noted that “when a patent claims a structure already known in the prior art that is altered by the mere substitution of one element for another known in the field, the combination must do more than yield a predictable results”. KSR International Co. v. Teleflex Inc., 550 U.S. 398 at 416, 82 USPQ2d 1385 (2007) at 1395 (citing United States v. Adams, 383 U.S. 39, 40 [148 USPQ 479] (1966)). See MPEP § 2143. In this case, one of ordinary skill in the art could have substituted a known conventional BLR circuit (e.g., comprising details such as “spacing of the set point voltages for the comparators 40 and 42” “causing a bidirectional counter 44 to count up or down”, in order to achieve a desired “incremental scale factor of the feedback loop”) for the BLR circuit of Riehl et al. and the results of the substitution would have been predictable. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a known conventional BLR circuit (e.g., comprising details such as the range detector circuit is configured to generate a first control signal applied to the counter circuit, if the range detector circuit evaluates the level of the integrator output signal being below the first threshold level, and to generate a second control signal applied to the counter circuit, if the range detector circuit evaluates the level of the integrator output signal being above the second threshold level, wherein the counter circuit is configured to increment the state of the counter circuit, if the counter circuit receives the first control signal, wherein the counter circuit is configured to decrement the state of the counter circuit, if the counter circuit receives the second control signal) as the BLR circuit of Riehl et al.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Riehl et al. (US 2023/0367025) in view of Steadman Booker et al. (US 2019/0170880).
In regard to claim 13 which is dependent on claim 4, the circuitry of Riehl et al. lacks an explicit description of details of the “… BLR circuit …” such as the counter circuit is configured to preset the state of the counter circuit, or a digital code is added to an output of the counter circuit for cancelling a static leakage current from a photon detector to be coupled to the input terminal. However, “… BLR circuit …” details are known to one of ordinary skill in the art (e.g., see “… X-ray detectors 42 may suffer from drawbacks, which may cause a baseline shift of the value of the process signal c. Therefore, there may be a need for correcting the detector signal 42 … providing a correction signal c may relate to initially set a correction signal …” in paragraphs 80 and 110 of Steadman Booker et al.). It should be noted that “when a patent claims a structure already known in the prior art that is altered by the mere substitution of one element for another known in the field, the combination must do more than yield a predictable results”. KSR International Co. v. Teleflex Inc., 550 U.S. 398 at 416, 82 USPQ2d 1385 (2007) at 1395 (citing United States v. Adams, 383 U.S. 39, 40 [148 USPQ 479] (1966)). See MPEP § 2143. In this case, one of ordinary skill in the art could have substituted a known conventional BLR circuit (e.g., comprising details such as “initially set a correction signal”, in order to achieve “correcting” “X-ray detectors 42”) for the BLR circuit of Riehl et al. and the results of the substitution would have been predictable. Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a known conventional BLR circuit (e.g., comprising details such as the counter circuit is configured to preset the state of the counter circuit, or a digital code is added to an output of the counter circuit for cancelling a static leakage current from a photon detector to be coupled to the input terminal) as the BLR circuit of Riehl et al.
Allowable Subject Matter
Claim(s) 6, 8, and 9 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the instant application is deemed to be directed to a nonobvious improvement over the invention disclosed in US 2023/0367025. The improvement comprises in combination with other recited elements: (a) the range detector circuit is configured so that a range between the first and second threshold level is provided with a hysteresis as recited in claim 6; (b) the output stage comprises a digital-to-analog converter to convert the digital output signal to an analog output voltage signal, an output terminal to provide the baseline restoration output signal, wherein the output stage comprises a summation block to provide a voltage summation signal being a representation of a sum of the integrator output signal and the analog output voltage signal, wherein the output stage comprises a transconductor stage being coupled to the output terminal, wherein the transconductor stage is configured to convert the voltage summation signal to the baseline restoration output signal as recited in claim 8; and (c) an output terminal to provide the baseline restoration output signal, wherein the output stage comprises a first transconductor stage to convert the integrator output signal to a first current signal, wherein the first transconductor stage has a first output node to provide the first current signal, and wherein the first output node is connected to the output terminal, wherein the output stage comprises a digital-to-analog converter to convert the digital output signal to a second current signal, wherein the digital-to-analog converter has a second output node to provide the second current signal, and wherein the second output node is connected to the output terminal as recited in claim 9.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2008/0042632 teaches a self-tracking analog-to-digital converter.
US 2010/0329425 teaches CT.
US 2012/0154032 teaches a feedback path comprising compensation circuitry for outputting a compensation signal.
US 2013/0284940 teaches a synchronizable baseline shift determination.
US 2016/0301399 teaches a baseline restore circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shun Lee whose telephone number is (571)272-2439. The examiner can normally be reached Monday-Friday.
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/SL/
Examiner, Art Unit 2884
/UZMA ALAM/Supervisory Patent Examiner, Art Unit 2884