Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Claim 25 is rejected as failing to define the invention in the manner required by 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Regarding claim 1, the method step “removing the second protective layer” on page 3, line 23 with “the second protective layer remain on the functional semiconductor layer stack and on the sidewall of the conductive layer, respectively” on page 4, line 1-2. A claim cannot require the same element to be both removed and present in the finished device. Claim 25 will be examine with the removal of limitation “removing the second protective layer” of claim 25 on page 3, line 23.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 25, 26, 28-31, and 33-38 is/are rejected under 35 U.S.C. 103 as being unpatentable over Young et al, US 20210288223 in view of Thompson et al, US 20200381588
Regarding claim 25, Young discloses : A method for processing an optoelectronic device, the method comprising: providing a functional semiconductor layer stack comprising an active region spaced apart from a surface of the functional semiconductor layer stack(Fig. 1a, #104n, #106, and #104p), the surface comprising a conductive layer deposited thereon(#105 disposed) on stack; depositing a patterned hard mask stack on the conductive layer(#108 disposed on #105), wherein the hard mask stack comprises at least a first mask layer(#108); dry etching the patterned hard mask stack and the conductive layer to provide a structured hard mask stack and to expose portions of the functional semiconductor layer stack(Fig. 1b, #105 and #108 etched to expose #104t); depositing a first protective layer at least on a sidewall of the conductive layer(Fig. 1c, #112 on a sidewall of #105), the first protective layer comprising similar etching properties as the first mask layer and being resilient to a wet chemical etching process(#112 may be made of the same materials as #108 [0052, 0057, 0058] ; first etching portions of the structured hard mask stack and the functional semiconductor layer stack not covered by the structured hard mask stack to a first depth exposing edges of the active region(Fig. 1d, etched to form mesa [0062] without changes of ##104 not covered by #108 from Fig. 1c); covering the exposed edges of the active region with a second protective layer(Fig. 1e, #114 covering exposed edges of #106); wherein side edges of the conductive layer are protected by the first protective layer(#112 on a sidewall of #105); second etching further portions of the structured hard mask stack and the functional semiconductor layer stack not covered by the structured hard mask to a second depth(Fig. 1f, second etch to expose #111); and further processing the optoelectronic device such that a portion of the first mask layer and the second protective layer remain on the functional semiconductor layer stack and on the sidewall of the conductive layer, respectively(Fig. 1g-1m, #108 remains on #104 and #114 on a sidewall of #105 and #104).
Young does not disclose : anisotropic dry chemical ; performing the wet chemical etching process.
However, in the same field of endeavor, Thompson teaches : anisotropic dry chemical etching(Fig. 12a-12f, dry etching to form mesa in #1210 [0126]; performing the wet chemical etching process(wet cleaning may be used before forming protective layer #1240 [0128]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Thompson to Young to use a dry etching technique to form a mesa in a micro-LED and a wet chemical etching process to perform surface reconstruction and minimize surface loss before the steps of forming a protective layer in the mesa (Thompson [0128]).
Regarding claim 26, Young as modified by Thompson discloses : The method according to claim 25.
Thompson teaches : wherein providing the functional semiconductor layer stack comprises: depositing a functional semiconductor layer stack(Fig. 12b, #1210); depositing a conductive material on the surface of the functional semiconductor layer stack(#1220); optional depositing an annealing layer on top of the conductive material; and depositing the conductive layer on the conductive material after removing the annealing layer on the conductive material(#1225 on #1220), the conductive layer being more compatible with a dry etching process used to structure the patterned hard mask or more resilient against KOH(#1225 may act as hard mask for dry etch [0126]).
Regarding claim 28, Young as modified by Thompson discloses : The method according to claim 25.
Young teaches : wherein the first protective layer comprises the same material as the first mask layer having a thickness on the sidewall in a range of 10 nm to 70 nm(#112 may comprise the same material as #108 [0052, 0058] #112 may have varying thicknesses [0061]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to choose a protective layer’s thickness to be in the range of 10nm to 70 nm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 29, Young as modified by Thompson discloses : The method according to claim 28.
Young teaches : wherein the first protective layer encapsulates the first mask layer of the structured hard mask stack and at least partially covers the exposed portions of the functional semiconductor layer stack(#112 disposed on a side of #108 and a top surface of exposed #104 [0057]).
Regarding claim 30, Young as modified by Thompson discloses : The method according to claim 25.
Young teaches : wherein first anisotropic dry chemical etching causes inclined sidewalls in the functional semiconductor layer stack(Fig. 1d, etching forms inclined trench #111).
Regarding claim 31, Young as modified by Thompson discloses : The method according to claim 25.
Young teaches : wherein the first depth is in a range between 300nm and 1000nm(Fig. 1e, #111 has a depth in the range of 0.5um to 2 um [0069]).
Regarding claim 33, Young as modified by Thompson discloses : The method according to claim 25.
Young teaches : wherein covering the exposed edges of the active region comprises depositing the second protective layer onto sidewalls using an ALD process having a thickness in a range smaller than 6o nm(Fig. 1e, #114 deposited on sidewall of #106 by ALD process [0065]. After deposition, #114 is etched to only be on a side surface).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to choose a protective layer’s thickness to be less than 60nm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 34, Young as modified by Thompson discloses : The method according to claim 25.
Thompson teaches :wherein second anisotropic dry chemical etching comprises the same etchant as the first anisotropic dry chemical etching, and/or wherein the second anisotropic dry chemical etching removes the second protective layer on top of the functional semiconductor layer stack(Fig. 1e, etching don’t so that #114 remains on a sidewall and not on a top surface of #111 of #104).
Regarding claim 35, Young as modified by Thompson discloses : The method according to claim 25.
Young teaches : wherein second anisotropic dry chemical etching causes inclined surface portions of the functional semiconductor layer stack(Fi.g 1d, #111 pixel pitch to have inclined surfaces [0067]).
Regarding claim 36, Young as modified by Thompson discloses : The method according to claim 25.
Thompson teaches : wherein second anisotropic dry chemical etching is performed until an undoped buffer layer of the functional semiconductor layer stack is reached, and/or wherein second anisotropic dry chemical etching removes portions of the first mask layer(Fig. 1f, etching of #104 process continues until it reaches #102t).
Regarding claim 37, Young as modified by Thompson discloses : The method according to claim 25, wherein the functional semiconductor layer stack comprises a semiconductor material from the group consisting of GaN, InGaN and InAlGaN(#104 comprised one or more of gallium (Ga), aluminum (Al), and indium (In) [0041]), and wherein optionally a crystal orientation of the semiconductor material is substantially inert to the wet chemical etching process.
Regarding claim 38, Young as modified by Thompson discloses : The method according to claim 25.
Thompson teaches : wherein further processing the optoelectronic device comprises: depositing a third protective layer using an ALD process on sidewalls and the surface encapsulating remaining portions of the first mask layer(Fig. 12f, #1240 on sidewalls and surface of #1230, #1220, and #1225), the conductive layer and the active region of the functional semiconductor layer stack(Fig 13b shows the location of active layer #1335); structuring the third protective layer and the remaining portion of the first mask layer to expose a portion of the conductive layer(Fig. 12k, #1240 removed to expose #1225); and depositing a metal layer on the third protective layer, electrically connecting the conductive layer(Fig. 12l, #1260 deposited to be connected to #1225 [0135]).
Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Young et al, US 20210288223 in view of Thompson et al, US 20200381588, in further view of Teo et al, US 20220173276.
Regarding claim 27, Young as modified by Thompson discloses : The method according to claim 25.
Young teaches : wherein depositing the patterned hard mask stack comprises: depositing the first mask layer of SiNx on the conductive layer (#108 may comprise silicon nitride [0052] and may be disposed on #105) optional depositing a second layer comprising SiO2 on the first mask layer, the second layer having a smaller thickness than the first mask layer; and depositing a photoresist and pattern the photoresist(Fig. 1b, patterned to form opening [0054]).
Young as modified by Thompson does not disclose : having a thickness in a range of larger than 5oonm.
However, in the same field of endeavor, Teo teaches : having a thickness in a range of larger than 5oonm(hard mask with thickness of 0.5x of semiconductor layers [0046, 0057].
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to select an appropriate thickness for a hardmask, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim(s) 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Young et al, US 20210288223 in view of Thompson et al, US 20200381588, in further view Margalith et al, US 20220005980.
Regarding claim 32, Young as modified by Thompson discloses : The method according to claim 25.
Young as modified by Thompson does not disclose : wherein the wet chemical etching process comprises etching with KOH.
However, in the same field of endeavor, Margalith teaches : wherein the wet chemical etching process comprises etching with KOH(wet chemical etching using KOH with device protected before etch [0061]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Margalith to Young and Thompson to use a wet chemical etching process comprising KOH to the etching process of Young after using a protective layer on a side surface of a conductive layer to remove unnecessary elements while providing protection.
Claim(s) 39 is/are rejected under 35 U.S.C. 103 as being unpatentable over Young et al, US 20210288223 in view of Thompson et al, US 20200381588, in further view of Chang et al, US 20170373228.
Regarding claim 39, Young as modified by Thompson discloses : The method according to claim 25.
Young as modified by Thompson does not disclose : wherein further processing the optoelectronic device comprises: encapsulating the optoelectronic device within a sacrificial layer; encapsulating the optoelectronic device with a filling material; forming an anchor by the filling material supporting the optoelectronic device, the anchor extending through the sacrificial layer; and removing the sacrificial layer.
However, in the same field of endeavor, Chang teaches : wherein further processing the optoelectronic device comprises: encapsulating the optoelectronic device within a sacrificial layer(Fig. 11, #162); encapsulating the optoelectronic device with a filling material(Fig. 12, #170); forming an anchor by the filling material supporting the optoelectronic device(#172 [0060]), the anchor extending through the sacrificial layer(#70 extends through #162); and removing the sacrificial layer(Fig 16, #162 removed [0063]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Chang to Young and Thompson to pick up and transfer LEDs from carrier substrate to a receiving substrate (Chang [0056]).
Claim(s) 40-48 is/are rejected under 35 U.S.C. 103 as being unpatentable over Young et al, US 20210288223 in view of Bono et al, US 20180315738.
Regarding claim 40, Young discloses : An optoelectronic device comprising: a functional layer stack comprising: a first doped layer; a second doped layer; an active region located between the first doped layer and the second doped layer(Fig. 5b, #104n and #104p with #106 in-between); a conductive layer located on a surface of the second doped layer(#105 on #104p); a structured non-conductive mask layer located on the conductive layer(#108 on #105); a structured protective layer located on the non-conductive mask layer(#112 on #108); and a metal layer located on the structured protective layer electrically connecting the conductive layer(#118p electrically connected through #125, #125 may be described as #325 [0106]).
Young discloses a two layer structure (#112 and #114) to cover sidewalls of a mask layer, conductive layer, and the active region but does not disclose : wherein the structured protective layer extends on sidewalls of the structured non- conductive mask layer, of the conductive layer and of the active region, and wherein a sidewall of the non-conductive mask layer is substantially flush with a sidewall of the conductive layer.
However, in the same field of endeavor, Bono teaches : wherein the structured protective layer extends on sidewalls of the structured non- conductive mask layer, of the conductive layer and of the active region(Fig. 1h, #130 extending along the sidewalls of #122, #119 [0079], and #118) , and wherein a sidewall of the non-conductive mask layer is substantially flush with a sidewall of the conductive layer(#sidewalls of #118 flushed with #119).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Bono to Young to provide insulation to layers with a protective layer (Bono [0096]).
Regarding claim 41, Young as modified by Bono discloses : The optoelectronic device according to claim 40.
Bono teaches : wherein a sidewall of the active region is flush with the sidewall of the conductive layer(Fig. 1h, sidewalls of #122 flushed with #119).
Regarding claim 42, Young as modified by Bono discloses : The optoelectronic device according to claim 40.
Bono teaches : wherein a second sidewall is laterally displaced to a sidewall of the active region and extends along a portion of the first doped layer(Fig. 1h, #138 along #130 extending along #124.
Regarding claim 43, Young as modified by Bono discloses : The optoelectronic device according to claim 42.
Young teaches : wherein an angle between the sidewall of the active region and the second sidewall is larger than 0°(Fig. 5b, angle between #112 and #114 greater than 0 degrees, where in #114 may be modified [0068]).
Regarding claim 44, Young as modified by Bono discloses : The optoelectronic device according to claim 40.
Young teaches : further comprising a material layer located between the sidewall of the conductive layer and the structured protective layer(#112 between #114 and #105), wherein the material layer comprises the same material as the structured non-conductive mask layer(#108 and #112 may include the same dielectric materials [0052, 0058]).
Regarding claim 45, Young as modified by Bono discloses : The optoelectronic device according to claim 44.
Young teaches : wherein the conductive layer comprises a first metal layer and a transparent conductive oxide(#105 may include #317 in another embodiment similar to #100 where #317 may include #305 and #311 where #311 may include transparent conductive oxides [0100-0102]).
Regarding claim 46, Young as modified by Bono discloses : The optoelectronic device according to claim 44.
Bono teaches : wherein the metal layer is positioned only on a top surface of the structured protective layer(Fig. 1g, #138 on a top surface of #130 [0092]).
Regarding claim 47, Young as modified by Bono discloses : The optoelectronic device according to claim 44.
Young teaches : wherein the structured protective layer comprises Al2O3(#112 may include aluminum oxide [0058]).
Regarding claim 48, Young as modified by Bono discloses : The optoelectronic device according to claim 40.
Young teaches : wherein a material of the structured non-conductive mask layer comprises SiNx(#108 may comprise silicon nitride [0052]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 20220384682 : Formation of mesa structure in micro-LEDs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVE TAN whose telephone number is (571)272-6841. The examiner can normally be reached M-F: 8-4 PST.
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/D.T./Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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