DETAILED ACTION
This is a first office action in response to application 18/728,088 filed 07/11/2024, in which claims 1-16 are presented for examination. A preliminary amendment was filed concurrently therewith providing amendments to claims 14-16 and adds new claim 17 is hereby acknowledged.
Currently claims 1-17 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 11, 13-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park U.S. Patent Application Publication No. 2017/0186363 A1 hereinafter Park.
Consider Claim 1:
Park discloses a shift register unit, comprising: (Park, See Abstract.)
an input module, configured to transmit an input signal of an input signal terminal to a first node in response to a first clock signal; (Park, [0062-0076], Fig. 3 items 341 and M1.)
a first control module, configured to transmit a first voltage signal to the first node in response to a second clock signal; (Park, [0062-0076], Fig. 3 items 341 and M2 and M3.)
a second control module, configured to transmit a second voltage signal to a second node in response to the first clock signal; (Park, [0062-0076], Fig. 3 item 342.)
a first output module, configured to transmit the first voltage signal to an output signal terminal in response to a signal of the second node; a second output module, configured to transmit the second clock signal to the output signal terminal in response to a signal of the first node; (Park, [0062-0076], Fig. 3 item 343)
a third control module, configured to transmit the first clock signal to the second node, or to transmit the first voltage signal to the first node in response to a control clock signal; (Park, [0062-0076], Fig. 3 item 344)
a first capacitor, connected between the first node and the output signal terminal; and a second capacitor, connected between the first voltage signal terminal and the second node. (Park, [0062-0076], Fig. 3 item C1 and C2)
Consider Claim 2:
Park discloses the shift register unit according to claim 1, wherein the input module comprises a first transistor, a control terminal of the first transistor is connected to a first clock signal line, a first terminal of the first transistor is connected to the input signal terminal, and a second terminal of the first transistor is connected to the first node. (Park, [0062-0076], Fig. 3 items 341 and M1, CLK1, CRY and Q1)
Consider Claim 3:
Park discloses the shift register unit according to claim 2, wherein the first control module comprises a second transistor and a third transistor; a control terminal of the second transistor is connected to a second clock signal line, and a second terminal of the second transistor is connected to the first node; a control terminal of the third transistor is connected to the second node, a first terminal of the third transistor is connected to a first voltage signal line, and a second terminal of the third transistor is connected to the first terminal of the second transistor. (Park, [0062-0076], Fig. 3 items 341 and Clk2, Q1, Q2, M2, and M3)
Consider Claim 4:
Park discloses the shift register unit according to claim 3, wherein the second control module comprises a fourth transistor and a fifth transistor, a control terminal of the fourth transistor is connected to the first clock signal line, a first terminal of the fourth transistor is connected to a second voltage signal line, and a second terminal of the fourth transistor is connected to the second node; a control terminal of the fifth transistor is connected to the first node, a first terminal of the fifth transistor is connected to a first output terminal of the third control module, and a second terminal of the fifth transistor is connected to the second node. (Park, [0062-0076], Fig. 3 items 341 and Clk1, M4, M5, VGL, Q1 and Q2.)
Consider Claim 5:
Park discloses the shift register unit according to claim 4, wherein the first output module comprises a sixth transistor, a control terminal of the sixth transistor is connected to the second node, a first terminal of the sixth transistor is connected to the first voltage signal line, and a second terminal of the sixth transistor is connected to the output signal terminal. (Park, [0062-0076], Fig. 3 items M6)
Consider Claim 6:
Park discloses the shift register unit according to claim 5, wherein the second output module comprises a seventh transistor, a control terminal of the seventh transistor is connected to the first node, a first terminal of the seventh transistor is connected to the second clock signal line, and a second terminal of the seventh transistor is connected to the output signal terminal. (Park, [0062-0076], Fig. 3 items M7)
Consider Claim 11:
Park discloses the shift register unit according to claim 1, wherein the first clock signal and the second clock signal are pulse signals with a same frequency and opposite phases. (Park, [0078], “Referring to FIGS. 3 and 4, the first clock signal CLK1 may have a period that is the same as a period of the second clock signal CLK2, and the second clock signal CLK2 may be a shifted signal by a half period (or, a horizontal time) with respect to the first clock signal CLK1.”)
Consider Claim 14:
Park discloses a gate drive circuit, comprising the shift register unit according to claim 1. (Park, [0042], “Referring to FIG. 1, the display device 1000 may include a display panel 100, a timing controller 200, a gate driver 300, and a data driver 500. The display device 1000 may further include an emission driver 400. For example, the display device 1000 may be an organic light emitting display device.”)
Consider Claim 13:
Park discloses the shift register unit according to claim 1, wherein the first voltage signal is at a high level, the second voltage signal is at a low level, and the input signal is a low-level start pulse signal. (Park, [0066], “The second switching element M2 may include a gate electrode receiving a signal of the second node Q2, a first electrode receiving the first DC voltage VGH, and a second electrode providing the first DC voltage VGH to the first node Q1.”)
Consider Claim 15:
Park discloses the gate drive circuit according to claim 14, wherein a plurality of the shift register units are electrically connected in a cascade manner, wherein an input signal terminal of a first-stage shift register unit is connected to a start pulse signal, and except for a last-stage shift register unit, an output signal terminal of each stage of the shift register unit is connected to an input signal terminal of a next-stage shift register unit. (Park, [0107], “The stages may sequentially output carry signals CRY[1] through CRY[6], gate initialization signals GI[1] through GI[6], and gate signals GW[1] through GW[6] when the frame start signal FLM having a logic low level is provided to the first stage SRC1. Each of the stages may simultaneously output the carry signals CRY[1] through CRY[6] and the gate initialization signals GI[1] through GI[6]. Because an output of the second output block 360 is dependent on an output of the first output block 340, the gate signals GW[1] through GW[6] output from the second output block 360 may be delayed (or shifted) by a horizontal time with respect to the carry signals CRY[1] through CRY[6] and the gate initialization signals GI[1] through GI[6].”)
Consider Claim 16:
Park discloses a display device, comprising the gate drive circuit according to claim 14. (Park, [0042], “Referring to FIG. 1, the display device 1000 may include a display panel 100, a timing controller 200, a gate driver 300, and a data driver 500. The display device 1000 may further include an emission driver 400. For example, the display device 1000 may be an organic light emitting display device.”)
Consider Claim 17:
Park discloses a display device, comprising the gate drive circuit according to claim 15. (Park, [0042], “Referring to FIG. 1, the display device 1000 may include a display panel 100, a timing controller 200, a gate driver 300, and a data driver 500. The display device 1000 may further include an emission driver 400. For example, the display device 1000 may be an organic light emitting display device.”)
Allowable Subject Matter
Claims 7-10 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Prior art made of record and not relied upon which is still considered pertinent to applicant's disclosure is cited in a current or previous PTO-892. The prior art cited in a current or previous PTO-892 reads upon the applicants claims in part, in whole and/or gives a general reference to the knowledge and skill of persons having ordinary skill in the art before the effective filing date of the invention. Applicant, when responding to this Office action, should consider not only the cited references applied in the rejection but also any additional references made of record.
In the response to this office action, the Examiner respectfully requests support be shown for any new or amended claims. More precisely, indicate support for any newly added language or amendments by specifying page, line numbers, and/or figure(s). This will assist The Office in compact prosecution of this application. The Office has cited particular columns, paragraphs, and/or line numbers in the applied rejection of the claims above for the convenience of the applicant. Citations are representative of the teachings in the art and are applied to the specific limitations within each claim, however other passages and figures may apply. Applicant, in preparing a response, should fully consider the cited reference(s) in its entirety and not only the cited portions as other sections of the reference may expand on the teachings of the cited portion(s).
Applicant Representatives are reminded of CFR 1.4(d)(2)(ii) which states “A patent practitioner (§ 1.32(a)(1) ), signing pursuant to §§ 1.33(b)(1) or 1.33(b)(2), must supply his/her registration number either as part of the S-signature, or immediately below or adjacent to the S-signature. The number (#) character may be used only as part of the S-signature when appearing before a practitioner’s registration number; otherwise the number character may not be used in an S-signature.” When an unsigned or improperly signed amendment is received the amendment will be listed in the contents of the application file, but not entered. The examiner will notify applicant of the status of the application, advising him or her to furnish a duplicate amendment properly signed or to ratify the amendment already filed. In an application not under final rejection, applicant should be given a two month time period in which to ratify the previously filed amendment (37 CFR 1.135(c) ).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J JANSEN II whose telephone number is (571)272-5604. The examiner can normally be reached Normally Available Monday-Friday 9am-4pm EST.
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/Michael J Jansen II/ Primary Examiner, Art Unit 2626
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