Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/12/24 was filed in a timely manner; thus, the submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) #1-4, 10-13, is/are rejected under 35 U.S.C. 102(a)(2) as being unpatentable by UCHIDA et al. (U.S. Pub. No, 2019/0288106), hereinafter referred to as "Uchida".
Uchida shows, with respect to claim #1, a silicon carbide semiconductor device comprising: a silicon carbide substrate (fig. #6, item 10) having a first principal surface (fig. #6, item 1) and a second principal surface (fig. #4, item 2) opposite to the first principal surface (paragraph 0037); a source electrode (fig. #4, item 14) a gate insulating film (fig. #4, item 15) (paragraph 0037, 0048); a gate electrode (fig. #4, item 27) provided on the gate insulating film so that the gate insulating film is interposed between the silicon carbide substrate and the gate electrode (paragraph 0061); and an interlayer insulating film (fig. #4, item 25) covering the gate electrode (paragraph 0061), wherein: the silicon carbide substrate includes: a drift region (fig. #4, item 12) having a first conductivity type (paragraph 0042, 0064); a body region (fig. #4, item 13) provided on the drift region and having a second conductivity type different from the first conductivity type (paragraph 0004, 0037); a source region (fig. #4, item 14) provided on the body region so as to be spaced apart from the drift region, and having the first conductivity type (paragraph 0037, 0048); and a contact region (fig. #4, item 18) provided on the body region and having the second conductivity type (paragraph 0068), a gate trench (fig. #4, item 6) is provided in the first principal surface, and is defined by a side surface penetrating the source region and the body region and reaching the drift region (paragraph 0037), and a bottom surface (Below, fig. #Ex1, item PGT) continuous with the side surface (Below, fig. #Ex1, item SS), the gate trench extending in a first direction parallel to the first principal surface, the source electrode is connected to the source region and the contact region, the gate insulating film makes contact with the side surface and the bottom surface, the silicon carbide substrate includes: an electric field mitigation region (fig. #8, item 92) provided between the bottom surface and the second principal surface, extending in the first direction, and having the second conductivity type (paragraph 0055, 0057); and a connection region (fig. #8, item 93) electrically connecting the contact region (fig. #4, item 18) and the electric field mitigation region (fig. #8, item 92), and having the second conductivity type, the electric field mitigation region includes: a first region (Below, fig. #Ex2, item 92b) having a first dimension (Below, fig. #Ex2, item FD2) in a second direction (Below, fig. #Ex2, item X) perpendicular to the first direction (Below, fig. #Ex2, item Y); and a second region (Below, fig. #Ex2, item 92a) connected to the first region in the first direction and having a second dimension (Below, fig. #Ex2, item SD) smaller than the first dimension in the second direction, a contact hole (Below, fig. #Ex1, item CH) is formed in the interlayer insulating film (Below, fig. #Ex1, item 25) (paragraph 0074), extends in the first direction, and exposes a portion of the source region (paragraph 0099), the contact region includes a third region exposed via the contact hole and connected to the source electrode (fig. #8, item 14) (paragraph 0037), in a plan view viewed in a direction perpendicular to the first principal surface, the gate trench and the electric field mitigation region overlap a virtual straight line extending in the first direction (paragraph 0037), the connection region makes contact with the electric field mitigation region (fig. #8, item 92) on the virtual straight line, and the first region and the third region are arranged side by side in the second direction (paragraph 0055, 0057).
[AltContent: arrow][AltContent: rect][AltContent: textbox (Contact Hole; CH)][AltContent: arrow][AltContent: textbox (Side Surface; SS)][AltContent: textbox (Trench Surface; PGT)][AltContent: arrow][AltContent: textbox (Ex1)]
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Uchida shows, with respect to claim #2, a silicon carbide semiconductor device wherein: in the plan view viewed in the direction perpendicular to the first principal surface, a portion of the first region and a portion of the third region overlap each other (Fig. #3 and 24) (paragraph 0077, 0112).
Uchida shows, with respect to claim #3, a silicon carbide semiconductor device wherein: in the plan view viewed in the direction perpendicular to the first principal surface, the third region has a first side extending in the first direction, and an entirety of the first side overlaps a portion of the first region (Fig. #3 and 24) (paragraph 0077, 0112).
Uchida shows, with respect to claim #4, a silicon carbide semiconductor device wherein: a plurality of the gate trenches are provided at constant intervals so as to overlap the virtual straight line, and the connection region is provided between adjacent gate trenches that are adjacent to each other in the first direction in the plan view viewed in the direction perpendicular to the first principal surface (Fig. #9 and 6) (paragraph 0077, 0082).
Uchida shows, with respect to claim #10, a silicon carbide semiconductor device wherein the contact region (fig. #4, item 18) includes the third region on both sides of the gate trench in the second direction (paragraph 0064).
Uchida shows, with respect to claim #11, a silicon carbide semiconductor device wherein the contact region (fig. #1, item 18) includes the third region only on one side of the gate trench (fig. #1, item 6) in the second direction (paragraph 0037, 0064).
Uchida shows, with respect to claim #12, a silicon carbide semiconductor device wherein a first effective concentration of an impurity of the second conductivity type (fig. #4, item 21)(paragraph 0064) in the contact region is higher than a second effective concentration of an impurity of the second conductivity type in the connection region (paragraph 0067-0068, 0091).
Uchida shows, with respect to claim #13, a silicon carbide semiconductor device wherein the side surface of the gate trench includes a {0-33-8} plane paragraph 0062, 0070).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) #5-9 are rejected under 35 U.S.C. 102(a)(2) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over UCHIDA et al. (U.S. Pub. No, 2019/0288106), hereinafter referred to as "Uchida".
Uchida shows, with respect to claim #5, a silicon carbide semiconductor device wherein: in the plan view viewed in the direction perpendicular to the first principal surface, the contact region further includes a fourth region (Fig. #3 and 9, item 50) (paragraph 0037) provided between the adjacent gate trenches that are adjacent to each other in the first direction, the third region (Fig. #3, item 60) has a third dimension in the first direction, and the fourth region (Fig. #3 and 9, item 50) has a fourth dimension in the first direction smaller than the third dimension (paragraph 0042, 0048).
The Examiner notes that Uchida does not explicitly state that there is a specific difference in size of the various areas shown in the claim language. However, the Examiner notes that the applicant has not established the critical nature of various components having a smaller size than accompanying components. “The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims. In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range.” In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir.1990). To establish unexpected results over a claimed range, applicants should compare a sufficient number of tests inside and outside the claimed range to show criticality of the claimed range. In re Hill, 284 F.2d 955, 128 USPQ 197(CCPA 1960). Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have various ranges. Furthermore, the Applicant has not disclosed that having a specific difference in thickness solves any stated problem or is for any particular purpose. Accordingly, the claim is obvious without showing that the claimed range(s) or differences in thicknesses achieve unexpected results relative to the prior art examples. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Uchida shows, with respect to claim #6, a silicon carbide semiconductor device wherein the third dimension is more than one times and six or less times the fourth dimension (paragraph 0042, 0048).
Uchida shows, with respect to claim #7, a silicon carbide semiconductor device wherein the source region (fig. #1, item 14) (paragraph 0061) and the third region are alternately provided in the first direction, and the third dimension is larger than a fifth dimension of the source region in the first direction (paragraph 0042, 0048).
Uchida shows, with respect to claim #8, a silicon carbide semiconductor device wherein : the source region and the third region are alternately provided in the first direction, and the third dimension is 0.2 times or more and 0.6 times or less a sum of the third dimension and a fifth dimension of the source region in the first direction (paragraph 0042, 0048).
The Examiner notes that Uchida does not explicitly state that there is a specific difference in size of the various areas shown in the claim language third dimension is 0.2 times or more and 0.6 times or less a sum. However, the Examiner notes that the applicant has not established the critical nature of various components having a third dimension is 0.2 times or more and 0.6 times or less a sum. “The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims. In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range.” In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir.1990). To establish unexpected results over a claimed range, applicants should compare a sufficient number of tests inside and outside the claimed range to show criticality of the claimed range. In re Hill, 284 F.2d 955, 128 USPQ 197(CCPA 1960). Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have various ranges. Furthermore, the Applicant has not disclosed that having a specific difference in thickness solves any stated problem or is for any particular purpose. Accordingly, the claim is obvious without showing that the claimed range(s) or differences in thicknesses achieve unexpected results relative to the prior art examples. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Uchida shows, with respect to claim #9, a silicon carbide semiconductor wherein device the fourth region (Fig. #3 and 9, item 50) (paragraph 0037) is exposed from the interlayer insulating film (fig. #4, item 25), and the source electrode (fig. #4, item 16) is also connected to the fourth region (paragraph 0061, 0064).
EXAMINATION NOTE
The rejections above rely on the references for all the teachings expressed in the text of the references and/or one of ordinary skill in the art would have reasonably understood or implied from the texts of the references. To emphasize certain aspects of the prior art, only specific portions of the texts have been pointed out. Each reference as a whole should be reviewed in responding to the rejection, since other sections of the same reference and/or various combinations of the cited references may be relied on in future rejections in view of amendments.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andre’ Stevenson whose telephone number is (571) 272 1683 (Email Address, Andre.Stevenson@USPTO.GOV). The examiner can normally be reached on Monday through Friday from 7:30 am to 4:30 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached on 571-272 2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Andre’ Stevenson Sr./
Art Unit 2899
09/08/2026
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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