Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-19, 22 are pending and have been examined.
Priority
Acknowledgment is made that the instant application is a 371 of PCT/CN2023/121348.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(1) that forms the basis for the rejection set forth in this Office action:
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention;
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1-2, 19, 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (WO 2023039830 A1 – hereinafter Wang).
Regarding Claim 1, Wang teaches an array substrate (see the entire document; Figs. 1-8C; specifically, ([0088] - [0114]), and as cited below), comprising a plurality of pixel driving circuits (Fig. 1):
wherein a respective pixel driving circuit of the plurality of pixel driving circuits comprises a driving transistor (Td – Fig. 3B – [0100]), a first light emitting control transistor (T4), and a third reset transistor (Tr2);
active layers of the driving transistor, the first light emitting control transistor, and the third reset transistor are in a first semiconductor material layer (SML1 – Fig. 4A – 4D – [0100]);
a first electrode (Sd – [0101]) of the driving transistor, a second electrode (D3) of the first light emitting control transistor (T4), and a second electrode of the third reset transistor (Tr2) are in the first semiconductor material layer (SML1 which are detailed in [0100]);
the first electrode of the driving transistor (Td), the second electrode of the first light emitting control transistor (T4), and the second electrode of the third reset transistor (Tr2) are parts of a unitary structure (see [0103]); and
the first electrode of the driving transistor (Td), the second electrode of the first light emitting control transistor (T4), and the second electrode of the third reset transistor (Tr2) are connected to each other by one or more portions of the first semiconductor material layer (see [0089], [0114] for details).
Regarding Claim 2, Wang teaches the array substrate of claim 1, further comprising: a first light emitting control electrode pad (ACP – [0121]) on the first semiconductor material layer; and a plurality of light emitting control signal lines (EM[n] – [0088] – Fig. 3A) on a side of the first light emitting control electrode pad away from the first semiconductor material layer; wherein the first light emitting control electrode pad comprises a gate electrode (GL_N[n]) of the first light emitting control transistor; and a respective light emitting control signal line of the plurality of light emitting control signal lines is connected to the first light emitting control electrode pad through a via (see [0088]).
Regarding Claim 22, Wang teaches a display apparatus, comprising the array substrate of claim 1, and one or more integrated circuits connected to the array substrate ([0035]).
Regarding Claim 19, Wang teaches an array substrate (see the entire document; Figs. 1-8C; specifically, ([0088] - [0114]), and as cited below), comprising a plurality of pixel driving circuits (Fig. 1):
wherein a respective pixel driving circuit (Fig. 3A) of the plurality of pixel driving circuits comprises:
a second node connecting line (N3 – Fig. 2 – [0089]), a first light emitting control transistor (T4), a third reset transistor (Tr2);
the second node connecting line (N3) is connected to a second electrode (upper electrode in Fig. 2) of the first light emitting control transistor (T4), and connected to a second electrode (left electrode of Tr2) of the third reset transistor (Tr2); and
the second node connecting line (N3) is in a same layer as active layers of the first light emitting control transistor and the third reset transistor ([0102], [0111], [0114]).
Allowable Subject Matter
Claims 3-18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner’s Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 3: The array substrate of claim 1, further comprising a second light emitting control electrode pad on the first semiconductor material layer; and a plurality of light emitting control signal lines on a side of the second light emitting control electrode pad away from the first semiconductor material layer; wherein the respective pixel driving circuit further comprises a second light emitting control transistor; the second light emitting control electrode pad comprises a gate electrode of the second light emitting control transistor; and a respective light emitting control signal line of the plurality of light emitting control signal lines is connected to the second light emitting control electrode pad through a via.
Regarding claim 4: The array substrate of claim 2, wherein the respective pixel driving circuit further comprises a storage capacitor comprising a first capacitor electrode and a second capacitor electrode; the first light emitting control electrode pad and the first capacitor electrode are in a first gate metal layer; the second capacitor electrode is in a second gate metal layer on a side of the first gate metal layer away from the first semiconductor material layer; the plurality of light emitting control signal lines are in a first signal line layer on a side of the second gate metal layer away from the first gate metal layer.
Claim 5 depends from claim 4.
Regarding claim 6: The array substrate of claim 1, further comprising a first voltage connecting pad and a plurality of first voltage supply lines;
wherein an active layer of the first light emitting control transistor, the first voltage connecting pad, and the plurality of first voltage supply lines are in three different layers; and
a respective first voltage supply line of the plurality of first voltage supply lines is connected to the first voltage connecting pad, and the first voltage connecting pad is connected to a first electrode of the first light emitting control transistor.
Claims 7-12 depend from claim 6.
Regarding claim 13: The array substrate of claim 1, wherein the respective pixel driving circuit further comprises a first reset transistor and a second reset transistor;
wherein the array substrate further comprises:
a plurality of third reset signal lines configured to provide a third reset signal to first electrodes of third reset transistors in the plurality of pixel driving circuits; and
a plurality of first reset signal lines configured to provide a first reset signal to first electrodes of first reset transistors in the plurality of pixel driving circuits, and/ or a plurality of second reset signal lines configured to provide a second reset signal to first electrodes of
second reset transistors in the plurality of pixel driving circuits;
wherein the plurality of first reset signal lines, the plurality of second reset signal lines, and the plurality of third reset signal lines extend along a direction substantially parallel to a first direction.
Regarding claim 14: The array substrate of claim 1, wherein the array substrate further comprises:
a plurality of third reset signal lines configured to provide a third reset signal to
first electrodes of third reset transistors in the plurality of pixel driving circuits;
a plurality of first low voltage supply lines;
a plurality of fourth reset signal lines;
a plurality of fifth reset signal lines;
a plurality of sixth reset signal lines; and
a plurality of second low voltage supply lines;
wherein the plurality of third reset signal lines and the plurality of first low
voltage signal lines extend along a direction substantially parallel to a first direction;
the plurality of fourth reset signal lines, the plurality of fifth reset signal lines, the
plurality of sixth reset signal lines, and the plurality of second low voltage supply lines extend
along a direction substantially parallel to a second direction;
the second direction is different from the first direction; and
the plurality of fourth reset signal lines, the plurality of fifth reset signal lines, the
plurality of sixth reset signal lines, and the plurality of second low voltage supply lines are in a
same layer on a side of the plurality of third reset signal lines and the plurality of first low
voltage signal lines away from the first semiconductor material layer.
Claims 15-16 depend from claims 14.
Regarding claim 17: The array substrate of claim 1, further comprising a first respective anode, a second respective anode, a third
respective anode, and a fourth respective anode;
wherein the first respective anode is an anode for a subpixel of a first color, the
second respective anode is an anode for a subpixel of a second color, the third respective anode
and the fourth respective anode are anodes for two subpixels of a third color;
an orthographic projection of the third respective anode on the base substrate at
least partially overlaps with an orthographic projection of two adjacent second voltage supply
lines of the plurality of second voltage supply lines on the base substrate, and at least partially
overlaps with an orthographic projection of one of a respective fourth reset signal line, a
respective fifth reset signal line, a respective sixth reset signal line, and a respective second low
voltage supply line on the base substrate; and
an orthographic projection of the fourth respective anode on the base substrate at
least partially overlaps with an orthographic projection of two adjacent second voltage supply
lines of the plurality of second voltage supply lines on the base substrate, and at least partially
overlaps with an orthographic projection of one of a respective fourth reset signal line, a
respective fifth reset signal line, a respective sixth reset signal line, and a respective second low
voltage supply line on the base substrate.
Claim 18 depends from claim 17.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM.
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/MOHAMMAD A RAHMAN/
Primary Examiner, Art Unit 2898
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