Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Marui et al. (Hereinafter Marui, US 2021/0367070).
In regards to independent claim 1, Marui teaches a semiconductor device comprising:
an SJ layer extending in a first direction in a plane and configured by alternately arraying a plurality of semiconductor regions of a first conductivity type and a plurality of semiconductor regions of a second conductivity type in a second direction orthogonal to the first direction (Marui, [0044], SJ Structure, Fig. 1-4);
a first drain layer of the first conductivity type electrically connected to the SJ layer on one end side in the first direction (Marui, 50, Fig. 1-4);
a channel layer of the second conductivity type provided on the SJ layer on the other end side in the first direction (Marui, 30, Fig. 1-4);
a first source layer of the first conductivity type provided on the channel layer (Marui, 40, Fig. 1-4); and
a first gate electrode provided on a side of the channel layer and the first source layer in the first direction with a first insulating layer interposed therebetween (Marui, 60, 65, Fig. 1-4).
In regards to dependent claim 2, Marui teaches the semiconductor device according to claim 1, wherein the first insulating layer is provided on the SJ layer with the first gate electrode embedded therein (Marui, 60, 65, Fig. 1-4).
In regards to dependent claim 10, Marui teaches wherein a depletion layer is formed in the semiconductor region of the first conductivity type of the SJ layer (Marui, [0024], Fig. 1-4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Marui in view of Sato et al. (hereinafter Sato, US 2016/0079416).
In regards to dependent claim 3, Marui teaches all limitations from claim 1. Marui fails to teach wherein the first gate electrode is provided between the channel layer and the first source. Sato teaches wherein the first gate electrode is provided between the channel layer and the first source layer, and the first drain layer. It would have been obvious to one of ordinary skill in the art, having the teachings of Marui and Sato before him before the effective filing date of the claimed invention, to modify the super junction transistor taught by Marui to include gate electrode between the source and drain of Sato in order to obtain a super junction transistor with a gate electrode between the source and drain. One would have been motivated to make such a combination because it reduces the one resistance.
Claim(s) 11, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Marui in view of Kitigawa et al. (hereinafter Kitigawa, US 2003/0183858).
In regards to dependent claim 11, Marui teaches all limitations from claim 1. Marui fails to teach wherein the SJ layer is provided on an interlayer insulating layer including an insulating material. Kitigawa teaches wherein the SJ layer is provided on an interlayer insulating layer including an insulating material (Kitigawa, 3, 12, and 13 Fig. 13). It would have been obvious to one of ordinary skill in the art, having the teachings of Marui and Kitigawa before him before the effective filing date of the claimed invention, to modify the super junction transistor taught by Marui to include the insulating layer of Kitigawa in order to obtain a super junction transistor deposited on an insulating layer. One would have been motivated to make such a combination because it reduces leakage current from the transistor.
In regards to dependent claim 12, Marui teaches all limitations from claim 1. Marui fails to teach the interlayer insulating layer is laminated with a semiconductor substrate, and the SJ layer is provided on a laminated substrate including the interlayer insulating layer and the semiconductor substrate. Kitigawa teaches wherein the interlayer insulating layer is laminated with a semiconductor substrate, and the SJ layer is provided on a laminated substrate including the interlayer insulating layer and the semiconductor substrate (Kitigawa, 3, 12, and 13 Fig. 13). It would have been obvious to one of ordinary skill in the art, having the teachings of Marui and Kitigawa before him before the effective filing date of the claimed invention, to modify the super junction transistor taught by Marui to include the insulating layer of Kitigawa in order to obtain a super junction transistor deposited on an insulating layer. One would have been motivated to make such a combination because it reduces leakage current from the transistor.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Marui in view of Kitigawa and Yokoyama (US 2012/0248544)
In regards to dependent claim 13, Marui in view of Kitigawa teach all limitations from claim 12. Marui fails to teach wherein the laminated substrate is provided with a pixel including a logic circuit or a photodiode. Yokoyama teaches wherein the laminated substrate is provided with a pixel including a logic circuit or a photodiode (Yokoyama, [0702]). It would have been obvious to one of ordinary skill in the art, having the teachings of Marui Kitigawa and Yokoyama before him before the effective filing date of the claimed invention, to modify the super junction transistor taught by Marui to include the pixel circuit of Yokoyama in order to obtain a super junction transistor used within a pixel circuit. One would have been motivated to make such a combination because it enables the pixel to be smaller thereby enabling a higher resolution screen.
Allowable Subject Matter
Claims 4-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM C TRAPANESE whose telephone number is (571)270-3304. The examiner can normally be reached Monday - Friday 7am-12pm & 8pm-10pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WILLIAM C TRAPANESE/Primary Examiner, Art Unit 2812
Prosecution Insights