DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/19/2024 was considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lomnitz US 2017/0195072 A1 in view of Martin US 2012/0310601 A1.
Regarding claim 1, Lomnitz discloses a high-bandwidth vector network analyzer system (fig. 1-6, par. [0046-[0072]) for transmitting (fig. 1, signal generator 105, par. [0051]) and receiving (fig. 1, receive channel 106, par. [0051]) vector signals (fig. 1, vector network analyzer, par. [0012], [0051]), the system comprising a transmitting channel, the transmitting channel comprising a multi-tone signal circuit structure (fig. 2b, dual digital-to-analog converter 213, dual antialias filters 214, quadrature modulator 215, par. [0057]), an input of the multi-tone signal circuit structure being connected to a digital signal processing module (fig. 2B, digital waveform memory 212, address counter 211, par. [0057]) the multi-tone signal circuit structure generating a multi-tone parallel signal (generating and outputting two digital signals in quadrature relation one to the other (I/Q), par. [0057]) and outputting a multi-tone RF signal to a receiving end; wherein the system further comprises a receiving channel (fig. 1, receive channel 106, par. [0051]), the receiving channel comprising multi-channel parallel digital downconverters group (fig. 3, periodic signal analyzing receiver 300, par. [0061]).
Lomnitz does not disclose multi-channel parallel digital downconverters group the multi-channel parallel digital downconverters group comprising a plurality of multi-channel parallel digital downconverters the inputs of the plurality of multi-channel parallel digital downconverters are respectively connected to a plurality of analogue-to-digital conversion modules and processing the plurality of audio signals in parallel.
Martin discloses multi-channel parallel digital downconverters group (fig. 2, elm. 200, par. [0033]) the multi-channel parallel digital downconverters group comprising a plurality of multi-channel parallel digital downconverters (fig. 2, elm. 225, par. [0033]) the inputs of the plurality of multi-channel parallel digital downconverters are respectively connected to a plurality of analogue-to-digital conversion modules (multiple analog-to-digital converters, par. [0035]) and processing the plurality of audio signals in parallel (par. [0035]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to simultaneously process digital down-conversion (DDC) functionality among multiple distributed acquisition components, as taught in Martin in modifying the apparatus of Lomnitz. The motivation would be to effectively process a number of acquisition segments stored in memory simultaneously in parallel. (see Martin: abs.).
Regarding claim 2, Lomnitz and Martin discloses the high-bandwidth vector network analyzer system for transmitting and receiving vector signals according to claim 1, Lomnitz discloses the wherein the multi-tone signal circuit structure (fig. 1, Network Analyzer 101, comprises at least one signal generator 105 for signal generation, par. [0051]) comprises a multi-tone signal generator (fig. 1, signal generator 105, par. [0051]), a two-way multi-tone signal processing circuit structure (fig. 2b, dual digital-to-analog converter 213, dual antialias filters 214, quadrature modulator 215, par. [0057]) and an adder, the multi-tone signal generator having an input connected to a digital signal processing module (fig. 2b, 210 for generating a frequency up-converted wideband signal frequency, digital waveform memory 212, address counter 211, par. [0057]) generating multi-tone parallel signals at the digital end to produce an I-way baseband signal and a Q-way baseband signal (generating and outputting two digital signals, par. [0057]), the two-way multi-tone signal processing circuit structure receives the I-way baseband signal and Q-way baseband signal, respectively, and performs multi-tone signal processing (fig. 2b, dual digital-to-analog converter 213, dual antialias filters 214, quadrature modulator 215, par. [0057]).
Lomnitz does not disclose said adder receives the signals output from the two-way multi-tone signal processing circuit structure, adds the signals and outputs a multi-tone radio frequency signal.
Martin discloses adder (fig. 2, elm. 215, par. [0033]) receives the signals output (digital samples, par. [0033]) from the two-way multi-tone signal processing circuit structure (fig. 2, elm. 205, par. [0033]), adds the signals and outputs a multi-tone radio frequency signal (fig. 2, summed coherent waveform 270, par. [0033]).
The references are combined for the same reason already applied in the rejection of claim 1.
Regarding claim 3, Lomnitz and Martin discloses the high-bandwidth vector network analyzer system for transmitting and receiving vector signals according to claim 2, Lomnitz discloses wherein the two-way multi-tone signal processing circuit structure (fig. 2b, dual digital-to-analog converter 213, dual antialias filters 214, quadrature modulator 215, par. [0057]) comprises a digital-to-analogue converter (213), a modulator and a mixer (fig. 2b, par. [0056]-[0058]) respectively, the digital-to-analogue converter of the two-way multi-tone signal processing circuit structure receives I-way baseband signals and Q- way baseband signals (fig. 2b, par. [0056]-[0058]), respectively (213), said modulator's input is connected to the digital-to- analogue converter, the mixer's input receives the signals of the output of the modulator as well as the signals of the local radio frequency source, and carries out the frequency mixing, both of the mixed signals of the fig. 2b, par. [0056]-[0058]).
Lomnitz does not disclose said adder.
Martin discloses adder (fig. 2, elm. 215, par. [0033]).
The references are combined for the same reason already applied in the rejection of claim 1.
Regarding claim 4, Lomnitz and Martin discloses the high-bandwidth vector network analyzer system for transmitting and receiving vector signals according to claim 1, Martin discloses wherein the receiving channel (fig. 2, elm. 202, par. [0035]) further comprises a memory module (fig. 2, elm. 220, par. [0036]), the outputs of the multi-channel parallel digital downconverters (fig. 2, elm. 225, par. [0033]) are connected to the memory module, and the outputs of thefig. 2, elm. 205, par. [0033]).
The references are combined for the same reason already applied in the rejection of claim 1.
Regarding claim 6, Lomnitz and Martin discloses the high-bandwidth vector network analyzer system for transmitting and receiving vector signals according to claim 1, Lomnitz discloses wherein the receiving channel (fig. 1, receive channel 106, par. [0051]) further comprises a fast Fourier transform module group (fig. 3a, elm. 303, par. [0061]), the fast Fourier transform module group comprising a plurality of fast Fourier transform modules, the inputs of the plurality of fast Fourier transform modules are respectively connected to a plurality of analogue-to-digital conversion modules (fig. 3a, elm. 301, par. [0061]), and the outputs of said plurality of fast Fourier transform modules are all connected to a memory module (par. [0021]).
Claim(s) 5 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lomnitz in view of Martin as applied to claim 1 above, and further in view of Xia et al. CN 102098004 A (hereinafter referred to as Xia).
Regarding claim 5, Lomnitz and Martin discloses the high-bandwidth vector network analyzer system for transmitting and receiving vector signals according to claim 1, Lomnitz discloses wherein the multi-channel parallel digital downconverters comprises N groups of digital downconverter modules, the N groups of digital downconverter modules (fig. 2, elm. 200, par. [0033]) connected in parallel, each of the groups of digital downconverter modules comprising a digital oscillator (NCO, par. [0038]), a first multiplier (fig. 2, elm. 235, par. [0033]), a second multiplier, a first FIR digital extraction filter fig. 6, elm. 615, par. [0062]), and a second FIR digital extraction filter (fig. 11, elm. 1105, par. [0103]),
Lomnitz and Martin do not disclose the digital oscillator outputs 2 channels of IQ baseband data to a first multiplier and a second multiplier, respectively, and thedigital extraction filter, and the first FIR digital extraction filter and the second FIR digital extraction filter output I-way and Q-way signals respectively.
Xia discloses digital oscillator outputs 2 channels of IQ baseband data to a first multiplier and a second multiplier , respectively, and thefig. 1, 4, par.[0002], [00004]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to variable bandwidth digital down-converter realization, as taught in in modifying the apparatus of Xia. The motivation would be the down-converter can effectively and quickly process the input middle-frequency signals and flexibly configure signal processing bandwidth for a large range (see Xia: par. abs.).
Regarding claim 8, Lomnitz, Martin and Xia discloses the high-bandwidth vector network analyzer system for transmitting and receiving vector signals according to claim
5, Lomnitz discloses wherein the output frequency of the digital oscillator is defined according to the measured frequency (par. [0014]).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lomnitz in view of Martin view of Xia as applied to claim 5 above, and further in Di Vita et al. US 3,641,509 A (hereinafter referred to as Di Vita).
Regarding claim 7, Lomnitz, Martin and Xia discloses the high-bandwidth vector network analyzer system for transmitting and receiving vector signals according to claim
5, Lomnitz discloses wherein where the number of the digital downconverter modules (fig. 3, periodic signal analyzing receiver 300, par. [0061]) is less than the number of channels of the multi-tone signal processing circuit structure (generating and outputting two digital signals in quadrature relation one to the other (I/Q), par. [0057]).
Lomnitz, Martin and Xia do not disclose the system is multiplexed using time- shared serial processing.
Di Vita discloses the system is multiplexed using time- shared serial processing (col. ln. 45-49).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide multiplexing technique for effecting time sharing, as taught in Di Vita in modifying the apparatus of Lomnitz, Martin and Xia. The motivation would be to provide hardware-saving (see Di Vita: col. ln. 45-49).
Conclusion
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/COURTNEY G MCDONNOUGH/Examiner, Art Unit 2858
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858 5/7/2026
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