DETAILED ACTION
This non-final action is responsive to communications: 02/26/2026.
Claims 1-10, and 21-25 are pending. Claims 1, and 21 are independent.
Election/Restrictions
Applicant’s election without traverse of claims 1-10 (group IIA) in the reply filed on 02/26/2026 is acknowledged. Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/26/2026. However, applicant added new claims 21-30 in reply filed 02/26/2026, and claims 26-30 is not being entered for the following reasons:
Election by Original Presentation (MPEP 821.03): Newly submitted claims 26-30 are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
Invention group IIA (elected) and claim group 26-30 (new) are related as combination and subcombination. Inventions in this relationship are distinct if it can be shown that (1) the combination as claimed does not require the particulars of the subcombination as claimed for patentability, and (2) that the subcombination has utility by itself or in other combinations (MPEP § 806.05(c)). In the instant case, the combination as claimed (group IIA) does not require the particulars of the subcombination (claim group 26-30) as claimed such as: 1) “…pre-discharge circuit coupled to the first read bit line, the pre-discharge circuit
being controlled by a first clock signal…”, 2) “…pre-charge circuit coupled to the second read bit line, the pre-charge circuit being controlled by a second clock signal, 3) clock signal functionality. Also, claim group 26-30 does not require such as: first read port, second read port specific structure. Further the subcombination of claim group 26-30 has separate utility (associated with port specific architecture) such as a system level or platform level function.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 26-30 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Therefore, claims 1-10, and 21-25 are pending in the application.
Examiner Notes
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Notice of Pre-AIA or AIA Status
4. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
No Priority
5. No priority claimed. See ADS.
Information Disclosure Statement
6. Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 05/ 31/ 2024, and 07/11/2025. All IDS has been considered.
Specification Objections
7. The Title is objected to because the title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested:
“MULTIPORT SRAM STRUCTURE AND MANUFACTURING METHOD THEREOF”
Applicant is requested to check other claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 102
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
10. Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mathur et al. (US 2022/0343970 A1).
Regarding independent claim 1, Mathur teaches a method (see para [0034], para [0008]), comprising: forming (although recited as a method of “forming” manufacturing, claims do not recite substantive steps and is indistinct from an apparatus structure, other than the mere presentation of form as a method of forming instead of a device) a first read pull-down transistor (Fig. 5: TD0) and a first read pass-gate transistor (Fig. 5: TC0) over a substrate at a first level height (Fig. 5: Tier 0 on base of 3D multi-ported memory. See also, para [0009]: base of “3D multi-ported memory architecture”),
wherein the first read pull-down transistor (Fig. 5: TD0) and the first read pass-gate transistor (Fig. 5: TC0) are of a first read port of a static random-access memory (SRAM) cell (Fig. 5 in context of para [0031]: “read ports” of SRAM); and
forming a second read pull-down transistor (Fig. 5: TD located at “additional upper Tier” not shown) and a second read pass-gate transistor (Fig. 5: TC located at “additional upper Tier” not shown) over the substrate at a second level height higher than the first level height (Fig. 5: “…more (Read Tier)”. See more Tiers associated with read ports. See para [0009]: “…3D multi-ported memory architecture scales well for additional read ports, and more read ports may be stacked on additional upper tiers that extend in the same 3D connection…”. para [0009], para [0031]: number of read ports can be large when additional read tiers are available),
wherein the second read pull- down transistor and the second read pass-gate transistor are of a second read port of the SRAM cell (Fig. 5 in context of para [0009]: supported multiple read ports).
Regarding claim 2, Mathur teaches the method of claim 1, wherein a footprint of the second read pull-down transistor overlaps with a footprint (footprint taken as lateral approximate layout area) of the first read pull-down transistor (Fig. 5 in context of para [0009], para [0031]: vertically stacked multiple Tiers containing said read port transistors would meet the limitation from lithography/ fabrication/ mask feasibility standpoint).
Claim Rejections - 35 USC § 103
11. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
12. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
13. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
14. Claims 3, and 9- 10 is/are rejected under 35 U.S.C. 103 as being obvious over Mathur et al. (US 2022/0343970 A1), in view of Salahuddin et al. (US 2023/0206996 A1).
Regarding claim 3, Mathur teaches the method of claim 1. Mathur is silent with respect to remaining provisions of this claim “…forming a first write pull-up transistor and a second write pull-up transistor over the substrate at the first level height, wherein the first and second write pull-up transistors are of a write port of the SRAM cell...”
Salahuddin teaches comprising:
forming a first write pull-up transistor and a second write pull-up transistor over the substrate at the first level height (Fig. 3, Fig. 5 in context of para [0049]),
wherein the first and second write pull-up transistors are of a write port of the SRAM cell (para [0049]).
Mathur and Salahuddin are in the same filed of endeavor of multiport SRAM construction, structure, manufacturing and they are in analogous field of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Salahuddin into the teachings of Mathur such that claimed SRAM apparatus with different Tiers can be implemented in order to reduce read/ write disturbance and improve operation speed.
Regarding claim 9, Mathur teaches the method of claim 1. Mathur is silent with respect to remaining provisions of this claim.
Salahuddin teaches method comprising: forming a back-side voltage source line over the substrate (para [0054], lines 16-21 in context of Fig. 5),
wherein the back-side voltage source line is electrically connected to a source/drain region of the first read pull-down transistor (Fig. 3, Fig. 5, para [0054]: upper terminal of Fig. 3: TD1 is electrically and operably coupled to VDD using Q node and via transistor VGD biasing control).
Salahuddin’s backside, front side arrangement of power lines, WLs and BLs allows for higher density of integration of SRAM cells.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Salahuddin into the teachings of Mathur such that interconnect structure can be employed to deliver good scaling of power and control signals.
Regarding claim 10, Mathur teaches the method of claim 9. Mathur is silent with respect to remaining provisions of this claim.
Salahuddin teaches method comprising forming a back-side ground line over the substrate (para [0054], lines 16-21 in context of Fig. 5),
wherein the back-side ground line is electrically connected to a source/drain region of the second read pull-down transistor (Fig. 3, Fig. 5, para [0054]: upper terminal of Fig. 3: TD2 is electrically and operably coupled to GND via transistor VGS biasing control).
Salahuddin’s backside, front side arrangement of power lines, WLs and BLs allows for higher density of integration of SRAM cells.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Salahuddin into the teachings of Mathur such that interconnect structure can be employed to deliver good scaling of power and control signals.
15. Claims 21-25 is/are rejected under 35 U.S.C. 103 as being obvious over Salahuddin et al. (US 2023/0206996 A1), in view of Mathur et al. (US 2022/0343970 A1).
Regarding independent claim 21, Salahuddin teaches a method (Fig. 1-Fig. 8, para [0009]: construction of “multiport memory cell”), comprising:
forming (although recited as a method of “forming” manufacturing, claims do not recite substantive steps and is indistinct from an apparatus structure, other than the mere presentation of form as a method of forming instead of a device), over a back side of a substrate, a back-side voltage source line (para [0054], lines 16-21 in context of Fig. 5: “…power rails…VDD… provided on the backside of the bottom tier substrate…”);
forming, over the back side of the substrate, a back-side ground line (para [0054], lines 16-21 in context of Fig. 5: “…power rails…GND… provided on the backside of the bottom tier substrate…”) electrically isolated from the back-side voltage source line (required isolation between VDD, VSS terminals/ pads using dielectrics, see e.g., para [0054], para [0046]);
forming, at a front side of the substrate, an SRAM bitcell (Fig. 1-Fig. 5: SRAM bit cell. Para [0041]: SRAM bit cell formed “on the substrate”) including a write port (para [0049]: “write port”. Fig. 3: INV1-INV2 latch write port associated with WWL), a first read port (Fig. 3:32-1 “first read port”, para [0049]), and a second read port (Fig. 3: 32-2 “second read port”, para [0049]);
forming the first read port at a first height level relative to the substrate and forming the second read port at a second height level different from the first height level (para [0016]: separate Tier for read ports);
electrically connecting the back-side voltage source line to a source/drain region of a first read pull-down transistor of the first read port (Fig. 3, Fig. 5, para [0054]: upper terminal of Fig. 3: TD1 is electrically and operably coupled to VDD using Q node and via transistor VGD control biasing); and
electrically connecting the back-side ground line to a source/drain region of a second read pull-down transistor of the second read port (Fig. 3, Fig. 5, para [0054]: upper terminal of Fig. 3: TD2 is electrically and operably coupled to GND via transistor VGS control biasing).
Salahuddin is silent with respect to “forming the first read port at a first height level relative to the substrate and forming the second read port at a second height level different from the first height level”.
Mathur teaches forming the first read port (Fig. 5: TD0, TC0) at a first height level (Fig. 5: Tier 0) relative to the substrate and forming the second read port (Fig. 5: TD, TC located at “additional upper Tier” not shown) at a second height level different from the first height level (Fig. 5: “…more (Read Tier)”. See more Tiers associated with read ports. para [0009]: “…3D multi-ported memory architecture scales well for additional read ports, and more read ports may be stacked on additional upper tiers that extend in the same 3D connection…”. para [0009], para [0031]: number of read ports can be large when additional read tiers are available).
Salahuddin and Mathur are in the same filed of endeavor of multiport SRAM construction, structure and they are in analogous field of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Mathur into the teachings of Salahuddin such that claimed SRAM apparatus can be implemented in order to improve operation speed with benefits e.g., “…multi-porting features in an area efficient manner that are able to scale well with the number of read/write ports…” (Mathur para [0002]).
Regarding claim 22, Salahuddin and Mathur teach the method of claim 21. Salahuddin teaches wherein the first read port (Fig. 3: 32-1) comprises the first read pull- down transistor (Fig. 3: TD1) and a first read pass-gate transistor (Fig. 3: transistor with RWL-1) connected in series (see e.g., Fig. 3).
Regarding claim 23, Salahuddin and Mathur teach the method of claim 21. Salahuddin teaches wherein the second read port (Fig. 3: 32-2) comprises the second read pull-down transistor (Fig. 3: TD2) and a second read pass-gate transistor (Fig. 3: transistor with RWL-2) connected in series (see e.g., Fig. 3).
Regarding claim 24, Salahuddin and Mathur teach the method of claim 21. Mathur teaches wherein, in a top view, a footprint of at least one transistor of the second read port overlaps a footprint of at least one transistor of the first read port (Fig. 5 in context of para [0009], para [0031]: vertically stacked multiple Tiers containing said read port transistors meet the limitation Fig. 5 in context of para [0009], para [0031]: vertically stacked multiple Tiers containing read said port transistors would meet the limitation from lithography/ fabrication feasibility standpoint).
Regarding claim 25, Salahuddin and Mathur teach the method of claim 21. Salahuddin teaches wherein the back-side voltage source line is a back-side VDD line and the back-side ground line is a back-side VSS line (para [0054]).
Allowable Subject Matter
Claims 4-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims listed, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations listed in the following:
Claims 4-5. The method of claim 3, further comprising: forming a first write pull-down transistor, a second write pull-down transistor, a first write pass-gate transistor, and a second write pass-gate transistor over the substrate at the second level height, wherein the first and second write pull-down transistors and the first and second write passgate transistors are of the write port of the SRAM cell.
Claim 6. The method of claim 1, wherein the first read pull-down transistor and the first read pass-gate transistor are of a first conductivity type, and the second read pull-down transistor and the second read pass-gate transistor are of a second conductivity type opposite to the first conductivity type.
Claims 7-8. The method of claim 6, wherein the first read pull-down transistor and the first read pass-gate transistor are of p-type metal-oxide-semiconductor (PMOS) transistors, and the second read pull-down transistor and the second read pass-gate transistor are of NMOS transistors.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
NELSON et al. (US 2018/0219015 A1) is applicable for all claims. NELSON teaches a semiconductor structure (para [0027], Fig. 3 “six-transistor…6T…SRAM memory cell…”) having a frontside and a backside (Fig. 3: FRONT, BACK. See also para [0033]), comprising: an SRAM cell (see Fig. 3: 305 and/or 300) that includes first and second pull-up (PU) transistors (Fig. 3: T5, T6), first and second pull-down (PD) transistors (Fig. 3: T3, T4), first and second pass-gate (PG) transistors (Fig. 3: T1, T2), and bit line (BL) conductors (Fig. 3: BL, BL#).
Liaw (US 2015/0243667 A1), Chiu et al. (US 2021/0343332 A1, Lin (US 2014/0003133 A1), and Wang et al. (US 2021/0305262 A1) disclosure applicable for all claims.
It is suggested that applicant consider all prior arts made of record.
Conclusion
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825