Prosecution Insights
Last updated: August 17, 2026
Application No. 18/731,176

SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM

Non-Final OA §102§103
Filed
May 31, 2024
Priority
Sep 11, 2023 — RE 10-2023-0120633
Examiner
KIM, TONG-HO
Art Unit
Tech Center
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
95%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allowance Rate
1034 granted / 1086 resolved
+35.2% vs TC avg
Minimal +1% lift
Without
With
+0.7%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 8m
Avg Prosecution
37 currently pending
Career history
1100
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
46.3%
+6.3% vs TC avg
§102
31.2%
-8.8% vs TC avg
§112
9.0%
-31.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1086 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 5/31/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-2 and 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gu (US 2019/0019807). Regarding claim 1, Gu discloses, in at least figures 5, 9B, and related text, a semiconductor device comprising: a first word line (GE0, [45], [104]) having a first electrode portion (thinner portion of GE0, [104], figures) and a first extension portion (thicker portion of GE0/181b, [64], [104], figures) extending from the first electrode portion (thinner portion of GE0, [104], figures); a second word line (GE1d, [45], [104]) having a second electrode portion (thinner portion of GE1d, [104], figures) disposed at a higher level than the first electrode portion (thinner portion of GE0, [104], figures) and a second extension portion (thicker portion of GE1d/181b, [64], [104], figures) extending from the second electrode portion (thinner portion of GE1d, [104], figures); a first vertical memory structure (VS, [52]) extending through the first electrode portion (thinner portion of GE0, [104], figures) and the second electrode portion (thinner portion of GE1d, [104], figures) in a vertical direction; and a first interconnection structure (184b, [64]) electrically connected to the first extension portion (thicker portion of GE0/181b, [64], [104], figures), wherein the first extension portion (thicker portion of GE0/181b, [64], [104], figures) includes: a first lower portion (thicker portion of GE0/GE0 portion under 181b, [104], figures) extending from the first electrode portion (thinner portion of GE0, [104], figures), and a first plug portion (181b, [64]) extending upwardly from at least one side of the first lower portion (thicker portion of GE0/GE0 portion under 181b, [104], figures) and connected to the first interconnection structure (184b, [64]), and wherein at least a portion of the first lower portion (thicker portion of GE0/GE0 portion under 181b, [104], figures) has a thickness greater than a thickness of the first electrode portion (thinner portion of GE0, [104], figures). Regarding claim 2, Gu discloses the semiconductor device of claim 1 as described above. Gu further discloses, in at least figures 5, 9B, and related text, the first lower portion (thicker portion of GE0/GE0 portion under 181b, [104], figures) includes a first thickness portion (thicker portion of GE0, [104], figures) and a second thickness portion (thicker portion of GE0 with graded thickness, [104], figures) having different thicknesses (figures). Regarding claim 5, Gu discloses the semiconductor device of claim 2 as described above. Gu further discloses, in at least figures 5, 9B, and related text, the first lower portion (thicker portion of GE0/GE0 portion under 181b, [104], figures) further includes a third thickness portion (GE0 portion under 181b, [104], figures), and wherein a thickness of the third thickness portion (GE0 portion under 181b, [104], figures) is less than a thickness of the first electrode portion (thinner portion of GE0, [104], figures) and is different from a thickness of the second thickness portion (thicker portion of GE0 with graded thickness, [104], figures). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gu (US 2019/0019807) in view of Lee (US 2022/0115390). Regarding claim 19, Gu discloses, in at least figures 5, 9B, and related text, a data storage system comprising: a semiconductor device, wherein the semiconductor device includes: a first word line (GE0, [45], [104]) having a first electrode portion (thinner portion of GE0, [104], figures) and a first extension portion (thicker portion of GE0/181b, [64], [104], figures) extending from the first electrode portion (thinner portion of GE0, [104], figures); a second word line (GE1d, [45], [104]) having a second electrode portion (thinner portion of GE1d, [104], figures) disposed at a higher level than the first electrode portion (thinner portion of GE0, [104], figures) and a second extension portion (thicker portion of GE1d/181b, [64], [104], figures) extending from the second electrode portion (thinner portion of GE1d, [104], figures); a first vertical memory structure (VS, [52]) extending through the first electrode portion (thinner portion of GE0, [104], figures) and the second electrode portion (thinner portion of GE1d, [104], figures) in a vertical direction; and a first interconnection structure (184b, [64]) electrically connected to the first extension portion (thicker portion of GE0/181b, [64], [104], figures), wherein the first extension portion (thicker portion of GE0/181b, [64], [104], figures) includes a first lower portion (thicker portion of GE0/GE0 portion under 181b, [104], figures) extending from the first electrode portion (thinner portion of GE0, [104], figures), and a first plug portion (181b, [64]) extending upwardly from at least one side of the first lower portion (thicker portion of GE0/GE0 portion under 181b, [104], figures) and connected to the first interconnection structure (184b, [64]), and wherein at least a portion of the first lower portion (thicker portion of GE0/GE0 portion under 181b, [104], figures) has a thickness greater than a thickness of the first electrode portion (thinner portion of GE0, [104], figures). Gu does not explicitly disclose a data storage system comprising: a semiconductor device including an input/output pad; a controller electrically connected to the semiconductor device through the input/output pad and configured to control the semiconductor device. Lee teaches, in at least figure 1 and related text, the device comprising a data storage system (1000, [21]) comprising: a semiconductor device (1100, [21]) including an input/output pad; a controller (1200, [28]) electrically connected to the semiconductor device through the input/output pad (1101, [27]) and configured to control the semiconductor device (1100, [21]), for the purpose of providing a three-dimensional semiconductor memory device whose stability and/or electrical properties are improved ([4]). Gu and Lee are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Gu with the specified features of Lee because they are from the same field of endeavor. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Gu to have the data storage system comprising: a semiconductor device including an input/output pad; a controller electrically connected to the semiconductor device through the input/output pad and configured to control the semiconductor device, as taught by Lee, for the purpose of providing a three-dimensional semiconductor memory device whose stability and/or electrical properties are improved ([4], Lee). Allowable Subject Matter Claims 3-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1, 2, and 3 that recite "at least a portion of the first plug portion has a thickness less than the thickness of the at least a portion of the first lower portion having the thickness greater than the thickness of the first electrode portion" in combination with other elements of the base claims 1, 2, and 3. Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 6 that recite "a first thickness portion vertically non-overlapping with the second vertical support structure; a second thickness portion covering the upper end of the second vertical support structure, and wherein the first thickness portion has a thickness greater than a thickness of the second thickness portion" in combination with other elements of the base claims 1 and 6. Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 7 that recite "a second vertical support structure disposed below the first lower portion of the first extension portion, wherein the second vertical support structure has an upper surface disposed at a lower level than an upper surface of the first electrode portion" in combination with other elements of the base claims 1 and 7. Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 8 that recite "a second vertical support structure disposed below the first lower portion of the first extension portion" in combination with other elements of the base claims 1 and 8. Claims 9-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 9 that recite "a first insulating spacer on a side surface of the first insulating pattern, wherein the first plug portion is disposed between the side surface of the first insulating pattern and the first insulating spacer" in combination with other elements of the base claims 1 and 9. Claims 11-18 are allowed because the prior art of record neither anticipates nor render obvious the limitations of the base claims 11 that recite "a second vertical support structure disposed below the first insulating pattern, and wherein the first lower portion includes: a first thickness portion disposed below the first insulating pattern and vertically non-overlapping with the vertical support structures; a second thickness portion disposed between the second vertical support structure and the first insulating pattern" in combination with other elements of the base claims 11. Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 19 and 20 that recite "a first thickness portion vertically non-overlapping with the second vertical support structure; a second thickness portion covering the upper end of the second vertical support structure, and wherein the first thickness portion has a thickness greater than a thickness of the second thickness portion" in combination with other elements of the base claims 19 and 20. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TONG-HO KIM/Primary Examiner, Art Unit 2811
Read full office action

Prosecution Timeline

May 31, 2024
Application Filed
Jul 21, 2026
Non-Final Rejection mailed — §102, §103
Aug 10, 2026
Interview Requested

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
95%
Grant Probability
96%
With Interview (+0.7%)
1y 8m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1086 resolved cases by this examiner. Grant probability derived from career allowance rate.

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