DETAILED ACTION
This correspondence is in response to the communications received May 31, 2024. Claims 1-9 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 5 and the claims that depend therefrom are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The recitation of,
“forming a resist film on a surface of the aluminum alloy film so as to have a thickness that completely covers the surface of the aluminum alloy film, including any convex-shaped defect at said surface; and
…
patterning the aluminum alloy film using the resist film as a mask”, lacks support in the disclosure to go from completely covering the aluminum alloy film with a resist film, to then patterning the aluminum alloy film. The drawings lack any evidence that the resist film when covering both aluminum alloy film and the defect, is patterned to provide a mask that ultimately patterns the aluminum alloy film and removes the defect, beyond the intermediate step shown in Figs. 14-16. It is unclear what occurs sequentially after the method setting forth the structure as detailed in claim 5. Figs. 18-21 appear to be labelled as “related art”. Essentially, how does the etch remove the defect and corresponding aluminum alloy portion when those two elements are covered by the resist?
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5, 7, 9 and the claims that depend therefrom are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The recitation, “forming a resist film on a surface of the aluminum alloy film so as to have a thickness that completely covers the surface of the aluminum alloy film, including any convex-shaped defect at said surface”, renders the claim indefinite, as it is unclear if the italicized portion is a positive recitation of the defect’s presence. It appears that “including any” could include that there is not a defect present at all. Absent the defect presence, would then open up the interpretation of claim 5, to be rejectable by prior art such as the prior art reference of Narazaki (US 2004/0124464) as shown in Figs. 21A-21C, where a photoresist 904 is formed over a surface of aluminum alloy film 820, and then patterns 820 to be only used as a source electrode when separated from gate electrode 812, by patterning by the photoresist used as an etch mask, see ¶ 0145.
The same rejection and rationale is applied to the independent claims 7 and 9, for the italicized indefinite language, “7. The method according to claim 6, wherein said any convex-shaped defect has a height not more than 8μm.”, “9. The method according to claim 8, wherein said any convex-shaped defect has a height not more than 10μm.”
Examiner offers that if the term “any” would be replaced with “a”, the 112b rejection would be overcome.
Relevant Prior Art
Jain et al. (US 10,096,533) Figs. 5A-5H, shown below. However the convex defects do not interact with a resist layer to be removed.
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Savas et al. (US 2013/0334511) Fig. 12, shown below, however no interaction occurs between a resist layer and the convex features.
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Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Figs. 1, 2, 5 and 6, a method of manufacturing a semiconductor device, the method comprising:
forming a surface structure (“a surface device structure that includes a MOS structure (step S2: first process). For example, first, the p-type base region 2, the n+-type emitter regions 3, and the p+-type contact regions 4 of the IGBT are formed.”, ¶ 0062, and “”) having a metal oxide semiconductor (MOS) structure in a semiconductor substrate including a surface region thereof (portion of MOS formed in upper surface of substrate 10);
forming an interlayer insulating film (9, ¶ 0057, “interlayer insulating film 109”, ¶ 0041) partially covering the surface structure (covering upper surface of 10);
forming an aluminum alloy film (“Al-Si film 33”, ¶ 0068) in contact with the surface structure (top of 10) and covering an entire area where the surface structure (entirety of top of 10), including the interlayer insulating film (33 on 9), is formed;
forming a resist film (“resist film 131”, ¶ 0048) on a surface of the aluminum alloy film (on 33) so as to have a thickness that covers the surface of the aluminum alloy film while exposing a convex-shaped defect formed at said surface (see Fig. 5, where 31 is formed around convex portion 36 of 33);
patterning the aluminum alloy film using the resist film as a mask (outcome shown in Fig. 6, where the convex 36 part of 33 is removed, along with 30a); and
removing the resist film (31 removal by step of Fig. 6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Narazaki (US 2004/0124464) in view of Nakata (US 2020/0090937).
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Regarding claim 5, the prior art of Narazaki discloses in Fig. 21A-21C, a method of manufacturing a semiconductor device (see title, “Power Semiconductor Device … And Method of Manufacturing …”), the method comprising:
forming a surface structure having a metal oxide semiconductor (MOS) structure (gate 811, ¶ 0121, diffusion regions of transistor including 610, 621, “621 of the power MOSFET.” ¶ 0117, 630, ¶ 0119, 840, ¶ 0111 etc.) in a semiconductor substrate (“substrate 600”, ¶ 0117, “silicon substrate 600”, ¶ 0132) including a surface region thereof (device formed, in part, in the upper surface region of 600);
forming an interlayer insulating film (“interlayer insulation film 860”, ¶ 0123) partially covering the surface structure (860 partially covers previously noted surface structure, see Fig. 21C);
forming an aluminum alloy film (“a source electrode (main electrode) 820 of, for example, conductive Al--Si is formed on the interlayer insulation film 860”, ¶ 0127, so 820 is patterned from the “conductive Al--Si” material layer. The “alloy” aspect will be addressed in the combination rejection below.) in contact with the surface structure (820 partially covers previously noted surface structure) and covering an entire area where the surface structure, including the interlayer insulating film, is formed (820, which is the source electrode, covers the entire area where a source active region is exposed for electrical connection. In the process step described in ¶ 0145, in the following excerpt, the Al—Si film is blanketed on entire surface, “Then, a conductive Al--Si film is deposited on the entire interlayer insulation film 860 by sputtering to fill in the gate contact hole 819 and the source contact holes 829, and a photoresist pattern 904 is formed on the Al--Si film, using photolithography techniques (see FIG. 21). Using the photoresist pattern 904 as a mask, etching is performed to form the gate aluminum electrode 812 and the source electrode 820 from Al--Si film in the previously described configuration (see FIG. 21).”);
forming a resist film (“a photoresist pattern 904 is formed on the Al--Si film”, ¶ 0145) on a surface of the aluminum alloy film (¶ 0145, and 904 on 820, the Al—Si film is ) so as to have a thickness that completely covers the surface of the aluminum alloy film (shown in Fig. 21C), including any convex-shaped defect at said surface (this limitation is interpreted as an optional limitation, where “including any” is a statement meaning, that “if” there happens to be a defect, or if there happens not to be a defect present. The interpretation of the two options, then selects the available option where the defect is not present.);
patterning the aluminum alloy film using the resist film as a mask (at the extent of the method sequence of Fig. 21C, the photoresist has acted as a mask in a patterning step to pattern the visible portion of remaining Al—Si film which is now formed into the source electrode pattern, “Then, a conductive Al--Si film is deposited on the entire interlayer insulation film 860 by sputtering to fill in the gate contact hole 819 and the source contact holes 829, and a photoresist pattern 904 is formed on the Al--Si film, using photolithography techniques (see FIG. 21). Using the photoresist pattern 904 as a mask, etching is performed to form the gate aluminum electrode 812 and the source electrode 820 from Al--Si film in the previously described configuration (see FIG. 21).” ¶ 0145); and
removing the resist film (“Thereafter, the photoresist pattern 904 is removed.”, ¶ 0145).
Narazaki does not disclose, “forming an aluminum alloy film”, since Narazaki does not explicitly state that the aluminum silicon conductor used for the source electrode is an “alloy”, however this combination of materials makes an alloy as disclosed by Nakata in ¶ 0052, “a film of the source electrode 8 made of aluminum, an aluminum alloy of aluminum and silicon, nickel or the like”.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “forming an aluminum alloy film”, as disclosed by Nakata in the system of Narazaki, for the purpose of utilizing a conductive material that is highly compatible with the silicon substrate to form an electrode that has a lower interface potential difference lessening an ohmic mismatch. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claims 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Narazaki (US 2004/0124464) in view of Nakata (US 2020/0090937) in view of Sogo et al. (US 2002/0027244).
Regarding claim 6, the prior art of Narazaki et al. disclose the method according to claim 5, however Narazaki does not disclose, “wherein the thickness of the resist film is in a range of 3.3μm to 4.0μm.”
Sogo discloses a resist film used in a photolithography patterning step of a FET device feature, with a resist thickness in a range from 3-5 micrometers, “resist film (thickness: from 3 .mu.m to 5 .mu.m)”, ¶ 0060.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein the thickness of the resist film is in a range of 3.3μm to 4.0μm.”, as disclosed by Sogo in the system of Narazaki, for the purpose of utilizing a significantly thick photoresist material for being able to maintain its integrity during a patterning etch to form a particular pattern used in the formation of a transistor. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 8, the prior art of Narazaki et al. disclose the method according to claim 5, however Narazaki does not disclose, “wherein the thickness of the resist film is in a range of 3.8μm to 4.0μm.”
Sogo discloses a resist film used in a photolithography patterning step of a FET device feature, with a resist thickness in a range from 3-5 micrometers, “resist film (thickness: from 3 .mu.m to 5 .mu.m)”, ¶ 0060.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein the thickness of the resist film is in a range of 3.8μm to 4.0μm.”, as disclosed by Sogo in the system of Narazaki, for the purpose of utilizing a significantly thick photoresist material for being able to maintain its integrity during a patterning etch to form a particular pattern used in the formation of a transistor. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-4 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4 of U.S. Application No. 18/585,576. Although the claims at issue are not identical, they are not patentably distinct from each other because the parent application contains each of the instant application’s claimed limitations.
It is noted here, that the repetition of the claim language in the following rejections will be included only when it is not readily apparent how the claims share similar limitations or when obviousness type rejection is required. When claim numbers are only stated, it should be readily apparent to the reader, which limitations are shared by the instant application and the parent application.
Claim limitation(s) of the instant application (IA)
Claim limitation(s) of the co-pending Application (which has been allowed on April 15, 2026)
1. A method of manufacturing a semiconductor device, the method comprising:
A. forming a surface structure having a metal oxide semiconductor (MOS) structure in a semiconductor substrate including a surface region thereof;
B. forming an interlayer insulating film partially covering the surface structure;
C. forming an aluminum alloy film in contact with the surface structure and covering an entire area where the surface structure, including the interlayer insulating film, is formed;
D. forming a resist film on a surface of the aluminum alloy film so as to have a thickness that covers the surface of the aluminum alloy film while exposing a convex-shaped defect formed at said surface;
E. patterning the aluminum alloy film using the resist film as a mask; and
F. removing the resist film.
1. A method of manufacturing a semiconductor device, the method comprising:
A. forming a surface structure having a metal oxide semiconductor (MOS) structure in a semiconductor substrate;
B. forming an interlayer insulating film partially covering the surface structure;
C. forming an aluminum alloy film in contact with the surface structure and covering an entire area where the surface structure, including the interlayer insulating film, is formed;
D. forming a resist film covering a surface of the aluminum alloy film so as to have a thickness partially exposing a convex-shaped defect on the aluminum alloy film;
E. patterning the aluminum alloy film using the resist film as a mask; and
F. removing the resist film.
2. The method according to claim 1, wherein the thickness of the resist film is in a range of 1.6μm to 3.1μm.
2. The method according to claim 1, wherein the thickness of the resist film is in a range of 1.6μm to 3.1μm.
3. The method according to claim 1, wherein the thickness of the resist film is in a range of 2.7μm to 2.9μm.
3. The method according to claim 1, wherein the thickness of the resist film is in a range of 2.7μm to 2.9μm.
4. The method according to claim 1, wherein the convex-shaped defect has a height of at least 5μm.
4. The method according to claim 1, wherein the convex-shaped defect has a height of at least 5μm.
5. A method of manufacturing a semiconductor device, the method comprising:
forming a surface structure having a metal oxide semiconductor (MOS) structure in a semiconductor substrate including a surface region thereof;
forming an interlayer insulating film partially covering the surface structure;
forming an aluminum alloy film in contact with the surface structure and covering an entire area where the surface structure, including the interlayer insulating film, is formed;
forming a resist film on a surface of the aluminum alloy film so as to have a thickness that completely covers the surface of the aluminum alloy film, including any convex-shaped defect at said surface;
patterning the aluminum alloy film using the resist film as a mask; and
removing the resist film.
N/A
6. The method according to claim 5, wherein the thickness of the resist film is in a range of 3.3μm to 4.0μm.
N/A
7. The method according to claim 6, wherein said any convex-shaped defect has a height not more than 8μm.
N/A
8. The method according to claim 5, wherein the thickness of the resist film is in a range of 3.8μm to 4.0μm.
N/A
9. The method according to claim 8, wherein said any convex-shaped defect has a height not more than 10μm.
N/A
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara B Green can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893
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