DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, corresponding to claims 1-13 and 21-27, in the reply filed on 8/7/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie (US 2020/0274000).
Regarding claim 1, Xie discloses, in FIGS. 14A-14B and in related text, a field effect transistor (FET) device, comprising:
a channel layer (602) disposed on a substrate (204), wherein the channel layer comprises both horizontal and vertical portions, and wherein the vertical portions of the channel layer connect adjacent ones of the horizontal portions;
a gate (1402) surrounding the channel layer; and
source/drain regions (1202) on opposite ends of the channel layer (see Xie, [0116], [0133], [0136])).
Claims 1-3, 7 and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ye (US 2022/0310787).
Regarding claim 1, Ye discloses, in FIG. 2 and in related text, a field effect transistor (FET) device, comprising:
a channel layer (203) disposed on a substrate (200), wherein the channel layer comprises both horizontal (204A, 204B, 204C) and vertical portions (205A, 205B), and wherein the vertical portions of the channel layer connect adjacent ones of the horizontal portions;
a gate (210) surrounding the channel layer; and
source/drain regions (208) on opposite ends of the channel layer (see Ye, [0028]).
Regarding claim 2, Ye discloses the device of claim 1.
Ye discloses wherein the channel layer comprises silicon (Si) (see Ye, [0070], [0076]).
Regarding claim 3, Ye discloses the device of claim 1.
Ye discloses wherein the channel layer is under tensile strain (see Ye, [0070], [0076]).
Regarding claim 7, Ye discloses the device of claim 1.
Ye discloses wherein the vertical portions (205A, 205B) of the channel layer connect every other pair of the horizontal portions (204A, 204B, 204C) of the channel layer from a same side, thereby resulting in the channel layer comprising sideways-facing U-shaped segments (see Ye, FIG. 2).
Regarding claim 9, Ye discloses the device of claim 1.
Ye discloses wherein portions of the gate (210) are present between the horizontal portions (204A, 204B ,204C) of the channel layer (see Ye, FIG. 2, [0070]).
Regarding claim 10, Ye discloses the device of claim 1.
Ye discloses herein the channel layer has a thickness of from about 4 nanometers to about 10 nanometers (see Ye, [0053]-[0054], [0076]).
Claims 11 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ye (US 2022/0310787).
Regarding claim 11, Ye discloses, in FIG. 2 and in related text, a field effect transistor (FET) device, comprising:
a channel layer (203) disposed on a substrate (200) and comprising tensile-strained silicon (Si), wherein the channel layer comprises both horizontal (204A, 204B, 204C) and vertical portions (205A, 205B), and wherein the vertical portions of the channel layer connect adjacent ones of the horizontal portions;
a gate (210) surrounding the channel layer in a gate-all-around configuration, wherein portions of the gate are present between the horizontal portions of the channel layer; and
source/drain regions (208) on opposite ends of the channel layer (see Ye, [0028], [0070], [0076]).
Regarding claim 13, Ye discloses the device of claim 11.
Ye discloses wherein the vertical portions (205A, 205B) of the channel layer connect every other pair of the horizontal portions (204A, 204B, 204C) of the channel layer from a same side, thereby resulting in the channel layer comprising sideways-facing U-shaped segments (See Ye, FIG. 2, [0039]).
Claims 1-2 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang (US 2022/0223706).
Regarding claim 1, Yang discloses, in FIGS. 21-22 and in related text, a field effect transistor (FET) device (T1), comprising:
a channel layer (CS1) disposed on a substrate (10), wherein the channel layer comprises both horizontal (P11) and vertical portions (P12), and wherein the vertical portions of the channel layer connect adjacent ones of the horizontal portions;
a gate (GS) surrounding the channel layer; and
source/drain regions (34P) on opposite ends of the channel layer (see Yang, [0039], [0049]-[0051]).
Regarding claim 2, Yang discloses the device of claim 1.
Yang discloses wherein the channel layer comprises silicon (Si) (see Yang, [0053]-[0054]).
Regarding claim 9, Yang discloses the device of claim 1.
Yang discloses wherein portions of the gate (GS) are present between the horizontal portions (P11) of the channel layer (see Yang, FIG. 21).
Claims 21 and 23-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang (US 2022/0223706).
Regarding claim 21, Yang discloses, in FIGS. 21-22 and in related text, a semiconductor structure, comprising:
a substrate (10);
a channel layer (CS1) disposed over the substrate, the channel layer comprising a first horizontal portion (P11), a second horizontal portion (P11), and a vertical portion (P12) connecting the first horizontal portion to the second horizontal portion;
a gate (GS) surrounding the channel layer;
a first source/drain region (34P) and a second source/drain region (34P) on opposite ends of the channel layer; and
a dielectric (42) separating each of the first source/drain region and the second source/drain region from the substrate (see Yang, [0028], [0051], [0070], [0076]).
Regarding claim 23, Yang discloses the structure of claim 21.
Yang discloses wherein the gate (GS) comprises a gate dielectric surrounding the channel layer and a workfunction-setting metal disposed on the gate dielectric (see Yang, [0035], [0050]).
Regarding claim 24, Yang discloses the structure of claim 21.
Yang discloses a first inner spacer (32) disposed between the gate (GS) and the first source/drain region (34P); and
a second inner spacer (32) disposed between the gate (GS) and the second source/drain region (34P) (see Yang, FIG. 22, [0035]).
Regarding claim 25, Yang discloses the structure of claim 21.
Yang discloses wherein the channel layer is a first channel layer (CS1 on the left), the gate is a first gate (GS on the left), and the dielectric is a first dielectric (42 on the left), the semiconductor structure further comprising:
a second channel layer (CS1 on the right) disposed over the substrate (10);
a second gate (GS on the right) surrounding the second channel layer; and
a second dielectric (28, 52) disposed between the first gate and the second gate, the second dielectric electrically isolating the first gate from the second gate (see Yang, FIG. 21, [0035]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2022/0223706) in view of Jung (US 2022/0199618).
Regarding claim 11, Yang discloses, in FIGS. 21-22 and in related text, a field effect transistor (FET) device, comprising:
a channel layer (CS1) disposed on a substrate and comprising silicon (Si), wherein the channel layer comprises both horizontal (P11) and vertical portions (P12), and wherein the vertical portions of the channel layer connect adjacent ones of the horizontal portions;
a gate (GS) surrounding the channel layer in a gate-all-around configuration, wherein portions of the gate are present between the horizontal portions of the channel layer; and
source/drain regions (34P) on opposite ends of the channel layer (see Yang, [0039], [0049]-[0053]).
Yang does not explicitly disclose a channel layer comprising tensile-strained silicon.
Jung teaches a channel layer comprising tensile-strained silicon (see Jung, [0068]).
Jung and Jung are analogous art because they both are directed to transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jung with the features of Jung because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Yang to include a channel layer comprising tensile-strained silicon, as taught by Jung, to increase carrier mobility and improve reliability and performance (see Jung, [0068]).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Jung (US 2022/0199618).
Regarding claim 22, Yang discloses the structure of claim 21.
Yang discloses wherein the channel layer comprises silicon (see Yang, [0052]-[0053]).
Yang does not explicitly disclose wherein the channel layer comprises tensile-strained silicon.
Jung teaches wherein the channel layer comprises tensile-strained silicon (see Jung, [0068]).
Jung and Jung are analogous art because they both are directed to transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jung with the features of Jung because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Yang to include wherein the channel layer comprises tensile-strained silicon, as taught by Jung, to increase carrier mobility and improve reliability and performance (see Jung, [0068]).
Allowable Subject Matter
Claims 4-6, 8, 12 and 26-27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of records, individually or in combination, do not disclose nor teach “wherein the vertical portions of the channel layer connect every adjacent pair of the horizontal portions of the channel layer from alternating sides, thereby resulting in a serpentine configuration of the channel layer” in combination with other limitations as recited in claim 4.
The prior art of records, individually or in combination, do not disclose nor teach “wherein the sideways-facing U-shaped segments are unconnected to one another” in combination with other limitations as recited in claim 8.
The prior art of records, individually or in combination, do not disclose nor teach “wherein the vertical portions of the channel layer connect every adjacent pair of the horizontal portions of the channel layer from alternating sides, thereby resulting in a serpentine configuration of the channel layer” in combination with other limitations as recited in claim 12.
The prior art of records, individually or in combination, do not disclose nor teach “wherein the vertical portion is a first vertical portion, wherein the channel layer further comprises a third horizontal portion, a fourth horizontal portion, and a second vertical portion connecting the third horizontal portion to the fourth horizontal portion, and wherein the first vertical portion and the second vertical portion are disposed on a same side of the channel layer, thereby resulting in the channel layer comprising a first sideways-facing U-shaped segment and a second sideways-facing U-shaped segment” in combination with other limitations as recited in claim 26.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHIH TSUN A CHOU whose telephone number is (408)918-7583. The examiner can normally be reached M-F 8:00-16:00 Arizona Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHIH TSUN A CHOU/Primary Examiner, Art Unit 2811
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