DETAILED ACTION
This Office Action is in response to Applicant’s application 18/731,426 filed on June 3, 2024 in which claims 1 to 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings submitted on June 3, 2024 have been reviewed and accepted by the Examiner.
Information Disclosure Statement
The Information Disclosure Statements (IDS), filed on June 3, 2024 and February 18, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein has been considered by the Examiner.
Priority
Receipt is acknowledged of paper submitted under 35 U.S.C. 119(a)-(d) or under 35 U.S.C. 120, 121, 365(c), or 386(c) which has been placed of record in the file.
Notation
References to patents will be in the form of [C:L] where C is the column number and L is the line number. References to pre-grant patent publications will be to the paragraph number in the form of [xxxx].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
PNG
media_image1.png
589
675
media_image1.png
Greyscale
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. 2023/0402512 (Wu) and U.S. 2021/0328013 (Ando).
Regarding claim 1
PNG
media_image2.png
607
802
media_image2.png
Greyscale
and referring to annotated Figures 1, 22A and 22B, Wu discloses a semiconductor device comprising:
a substrate, 100 [0017], provided with an active pattern, 102 [0018], extending in a first horizontal direction parallel to an upper surface of the substrate, as annotated and shown;
a plurality of nanosheets, 104 [0018], disposed on the active pattern, as shown, and stacked to be spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate, as annotated and shown;
a gate electrode, 112 [0018] / 246 [0059], disposed on the active pattern, as shown, and extending in a second horizontal direction parallel to the upper surface of the substrate, as annotated, and shown, and different from the first horizontal direction, i.e., orthogonal, the gate electrode surrounding each of the plurality of nanosheets, as shown;
a source/drain region 108 [0019] / 232 [0074], disposed on the active pattern and disposed on a first side of the gate electrode, as shown;
a first inner spacer, 230 [0044], disposed between the source/drain region and a first portion of the gate electrode, as annotated and shown, disposed in a space between two adjacent nanosheets of the plurality of nanosheets, as shown, the first inner spacer contacting the source/drain region, as shown, and the first portion of the gate electrode being lower than an upper surface of the source/drain region, as annotated and shown.
PNG
media_image3.png
824
546
media_image3.png
Greyscale
Wu does not teach a second inner spacer disposed between the first inner spacer and the first portion of the gate electrode, the second inner spacer including a material different from a material of the first inner spacer, and each of an upper surface and a lower surface of the second inner spacer contacting the first inner spacer.
Ando is directed to improvement in GAA devices. At annotated Figure 9 and 10A, Ando teaches a first inner spacer, 111 e.g., SiN [0054], disposed between the source/drain region, 120 [0057], and a first portion of the gate electrode, as annotated and shown, disposed in a space between two adjacent nanosheets of the plurality of nanosheets, as shown, the first inner
PNG
media_image4.png
694
503
media_image4.png
Greyscale
spacer contacting the source/drain region, as shown, and the first portion of the gate electrode being lower than an upper surface of the source/drain region, as annotated and shown; and a second inner spacer, 110 [0055] e.g., SiC [0048] disposed between the first inner spacer, 111, and the first portion of the gate electrode, as shown, the second inner spacer including a material different from a material of the first inner spacer, SiC is not SiN, and each of an upper surface and a lower surface of the second inner spacer contacting the first inner spacer, as shown.
At [0062] Ando teaches referencing Applicant’s 2nd spacer as the 1st spacer 110;
[0062] As noted above, differences in Vt between high and low Vt devices are achieved by variances in work function metal thickness and/or presence near channel edges, while the work function metal thickness and/or presence at locations corresponding to the middle of the channel portions is the same for high and low Vt devices. The pinching-off of deposited work function metal between the first inner spacers 110 and channel layers (e.g., Si layers 104) permits reduced gate metal thickness and/or presence near channel edges of high Vt devices. For a high Vt device, the first inner spacers 110 remain to permit the pinching-off so that a thickness of work function metal is greater in areas corresponding to central portions of the plurality of channel layers than in areas corresponding to edge portions of the plurality of channel layers. For a low Vt device, the first inner spacers 110 are removed prior to metal deposition so that gate metal thickness and/or presence near channel edges is higher for low Vt devices than for high Vt devices.
[0033] According to an embodiment, an n-type work function metal includes a titanium nitride (TiN) and an aluminum-containing alloy (e.g. TiAlC). Due to the first set of inner spacers, the aluminum-containing alloy is absent near channel edges due to the pinch off of the TiN film for high Vt devices. Due to the first set of inner spacers, a p-type work function metal includes TiN, which is pinched-off and thinner near channel edges for the high Vt devices.
[0034] Differences in Vt are achieved by variances in work function metal thickness and/or presence near channel edges between high and low Vt devices, while the work function metal thickness and/or presence at locations corresponding to the middle of the channel portions is the same for high and low Vt devices.
Taken as a whole the prior art is directed to improvements in GAA transistors. Ando teaches the use of the second inner spacer enables the gate work function metal to be pinched off, which in turn modulates the differences in threshold voltages (Vt) as between n and p devices. An artisan would like to match the threshold of n and p devices to improve circuit performance and Ando teaches that pinching off the WF metal with the second inner spacer is a mechanism to tailor threshold voltage of the high voltage transistor.
Accordingly it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 1 with a second inner spacer disposed between the first inner spacer and the first portion of the gate electrode, the second inner spacer including a material different from a material of the first inner spacer, and each of an upper surface and a lower surface of the second inner spacer contacting the first inner spacer, as taught by Ando, to modulate the work function of the device, as taught by Ando, thus improving circuit performance and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Regarding claim 2 which depends upon claim 1, Ando teaches the second inner spacer is spaced apart from each of the plurality of nanosheets in the vertical direction at Figure 9.
Regarding claim 3 which depends upon claim 1, Ando teaches the second inner spacer is spaced apart from the source/drain region in the first horizontal direction, i.e. the first inner spacer is between the second inner spacer and the source/drain region.
Regarding claim 8 which depends upon claim 1, Ando teaches at least a part of the first inner spacer between the plurality of nanosheets overlaps the first portion of the gate electrode in the vertical direction, i.e., the electrode fills the empty space in Figure 9 resulting in the electrode butting up against 111 and 110 in a vertical direction.
Allowable Subject Matter
Claims 4-7 and 9-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 4 the prior art does not teach the device of claim 1, further comprising a gate insulating layer disposed in a space between an upper nanosheet of the two adjacent nanosheets and the first portion of the gate electrode a space between a lower nanosheet of the two adjacent nanosheets and the first portion of the gate electrode, the dielectric will surround all the suspending nanosheets creating a space, and a space between the second inner spacer and the first portion of the gate electrode, and wherein the gate insulating layer contacts the two adjacent nanosheets, the first portion of the gate electrode, the first inner spacer, and the second inner spacer.
Claims 5-6 depend directly on claim 5 and are allowable on that basis.
Regarding claim 7 the prior art does not teach the device of claim 1, wherein a side wall of the source/drain region contacting the first inner spacer is closer to the first portion of the gate electrode than side walls of the two adjacent nanosheets in the first horizontal direction wherein the side walls of the two adjacent nanosheets are adjacent to the first side of the gate electrode in the first horizontal direction.
Regarding claim 9 the prior art does not teach the device of claim 1, wherein a side wall of the first inner spacer contacting the source/drain region is formed in a concave shape toward the first portion of the gate electrode.
Regarding claim 10 the prior art does not teach the device of claim 1, wherein a side wall of the first inner spacer contacting a portion of the source/drain region is formed in a convex shape toward the portion of the source/drain region, and wherein the portion of the source/drain region is disposed in the space between the two adjacent nanosheets of the plurality of nanosheets.
Claims 11-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 11, the prior art fails to disclose the device of claim 11 wherein the first portion of the gate electrode is lower than the upper surface of the substrate; a source/drain region disposed on the active pattern and disposed on a first side of the gate electrode; a first inner spacer disposed in a space between the source/drain region and the gate insulating layer between the two adjacent nanosheets of the plurality of nanosheets, the first inner spacer including a first side wall contacting the source/drain region, and a second side wall contacting the gate insulating layer; and a second inner spacer disposed in a space between the first inner spacer and the gate insulating layer between the two adjacent nanosheets of the plurality of nanosheets, the second inner spacer including a material different from a material of the first inner spacer, the second inner spacer including a first side wall contacting the first inner spacer and a second side wall contacting the gate insulating layer, and the second inner spacer spaced apart from each of the plurality of nanosheets in the vertical direction, where Examiner notes the dictionary definition of ‘contact’ as requiring a ‘union or junction of surfaces’. See Ex parte Hwang, No. 2020-003817 (P.T.A.B. June 2, 2021) at 6-7.
Claims 12-19 depend directly or indirectly on claim 11 and are allowable on that basis.
Regarding claim 20, the prior art fails to disclose the device of claim 20 wherein a side wall of the second inner spacer being in contact with the gate insulating layer, and each of an upper surface and a lower surface of the second inner spacer being in contact with the first inner spacer, wherein the second inner spacer is spaced apart from each of the plurality of nanosheets in the vertical direction, wherein the second inner spacer is spaced apart from the source/drain region in the first horizontal direction, wherein a side wall of the first inner spacer being in contact with the source/drain region is formed in a concave shape toward the gate electrode, and wherein the side wall of the second inner spacer being in contact with the gate insulating layer is formed in a concave shape toward the source/drain region.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is listed on the notice of references cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joe Schoenholtz whose telephone number is (571)270-5475. The examiner can normally be reached M-Thur 7 AM to 7 PM PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ms. Yara Green can be reached at (571) 272-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.E. Schoenholtz/Primary Examiner, Art Unit 2893
Prosecution Insights