DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/3/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chao et al. (US Publication No. 2010/0229383).
Regarding claim 1, Chao discloses a semiconductor test structure (30) comprising:
a first surface (top) comprising a plurality of first conductive contacts (32) spaced apart from each other at a first pitch (PB)
a second surface (bottom) located opposite the first surface and comprising a plurality of second conductive contacts (60) spaced apart from each other at a second pitch (PT)
wherein the second pitch (PT) is less than the first pitch (PB)
wherein respective ones of the plurality of first conductive contacts (32) are electrically connected (90) to one or more respective ones of the plurality of second conductive contacts (60)
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Regarding claim 2, Chao discloses the respective ones of the plurality of first conductive contacts (32) are electrically connected to the one or more respective ones of the plurality of second conductive contacts (60) via one or more circuits (90) (paragraph 41).
Regarding claim 3, Chao discloses a plurality of wires electrically connecting the respective ones of the plurality of first conductive contacts (32) to the one or more respective ones of the plurality of second conductive contacts (60).
Regarding claim 4, Chao discloses the respective ones of the plurality of second conductive contacts (60) are configured to electrically contact respective ones of a plurality of third conductive contacts (52) of a device under test (DUT).
Regarding claim 5, Chao discloses the second pitch (PT) is the same as a pitch at which the respective ones of the plurality of third conductive contacts (52) are spaced apart (PT) from each other (Figure 8).
Regarding claim 6, Chao discloses the plurality of first conductive contacts comprise at least one of a plurality of conductive pads and a plurality of conductive bumps (paragraph 30).
Regarding claim 7, Chao discloses the plurality of second conductive contacts (60) comprise at least one of a plurality of probe tips, a plurality of scrub tips, a plurality of pins, a plurality of vias, a plurality of pillars and a plurality of wires (paragraph 32).
Regarding claim 8, Chao discloses the first pitch (PB) is the same as a pitch at which respective ones of a plurality of test probes (23) are spaced apart from each other (paragraph 42).
Regarding claim 9, Chao discloses one or more circuits, wherein the one or more circuits (90) comprise at least one of a phase locked loop circuit, a microcontroller, a built-in self-test engine and a sensor (paragraph 41).
Regarding claim 10, Chao discloses a redistribution layer, wherein the one or more circuits (90) are wired to the redistribution layer (31), and wherein the redistribution layer is configured to distribute one or more signals applied to the one or more circuits (90) to one or more interconnects of a device under test (paragraph 40).
Regarding claim 11, Chao discloses the respective ones of the plurality of first conductive contacts (32) are electrically connected to the one or more respective ones of the plurality of second conductive contacts (60) via the one or more circuits (90).
Regarding claim 12, Chao discloses the semiconductor test structure (30) is configured to be bonded to and de-bonded from a device under test (paragraph 32).
Regarding claim 13, Chao discloses the semiconductor test structure (30) is configured to be bonded to a silicon probe card (20).
Regarding claim 14, Chao discloses a semiconductor test structure (30) comprising:
a plurality of first conductive contacts (32) disposed on a first side (top) of the semiconductor test structure, wherein the plurality of first conductive contacts (32) are spaced apart from each other at a first pitch (PB)
a plurality of second conductive contacts (60) spaced apart from each other at a second pitch (PT) and disposed on a second side (bottom) of the semiconductor test structure
wherein the second side (bottom) is located opposite the first side (top)
wherein the second pitch (PT) is less than the first pitch (PB)
wherein respective ones of the plurality of first conductive contacts (32) are electrically connected (90) to one or more respective ones of the plurality of second conductive contacts (60)
Regarding claim 15, Chao discloses the respective ones of the plurality of first conductive contacts (32) are electrically connected to the one or more respective ones of the plurality of second conductive contacts (60) via one or more circuits (90) (paragraph 41).
Regarding claim 16, Chao discloses the respective ones of the plurality of second conductive contacts (60) are configured to electrically contact respective ones of a plurality of third conductive contacts (52) of a device under test (DUT).
Regarding claim 17, Chao discloses the second pitch (PT) is the same as a pitch at which the respective ones of the plurality of third conductive contacts (52) are spaced apart from each other.
Regarding claim 18, Chao discloses a semiconductor test structure comprising:
a first substrate (30) bonded to a second substrate (51)
a plurality of first conductive contacts (32) disposed on a first side of the first substrate (30), wherein the plurality of first conductive contacts are spaced apart from each other at a first pitch (PB)
a plurality of second conductive contacts (60) spaced apart from each other at a second pitch (PT) and disposed on a second side of the first substrate (30)
wherein the second side (bottom) is located opposite the first side (top)
wherein the second pitch (PB) is less than the first pitch (PT)
wherein respective ones of the plurality of first conductive contacts (30) are electrically connected (90) to one or more respective ones of the plurality of second conductive contacts (60)
wherein the second substrate (51) comprises a plurality of third conductive contacts (52) of a device under test (DUT) and the respective ones of the plurality of second conductive contacts (60) electrically contact respective ones of the plurality of third conductive contacts (52)
Regarding claim 19, Chao discloses the respective ones of the plurality of third conductive contacts (52) are spaced apart from each other at the second pitch (PT).
Regarding claim 20, Chao discloses the respective ones of the plurality of first conductive contacts (32) are electrically connected to the one or more respective ones of the plurality of second conductive contacts (60) via one or more circuits (90) (paragraph 41).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lewinnek et al. (US Publication No. 2025/0258219) discloses a test system (10) which reduces pitch to electrical connectors (20) on a DUT (12). Smith et al. (US Patent No. 7,368,927) discloses a reduced pitch probe head for testing a chip (Figure 12).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEIL R PRASAD whose telephone number is (571) 270-3129. The examiner can normally be reached M-F 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/N.R.P/ 8/2/2026 Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
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