DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (United States Patent Application Publication No. US 2010/0112753 A1, hereinafter “Lee”) in view of Zheng et al. (United States Patent Application Publication No. US 2018/0040374 A1, hereinafter “Zheng”) and further in view of Ding et al. (USPN 6,630,397 B1, hereinafter “Ding”).
In reference to claim 9, Lee discloses a similar device. Figure 3 of Lee discloses an integrated assembly which comprises a DRAM memory cell that includes a pillar comprising a first source/drain (206), a second source/drain (204), a third source/drain (202), a first channel (205) between the first source/drain (206) and the second source/drain (204), and a second channel (203) between the second source/drain (204) and the third source/drain (202). A first gate ((220) – near (205)) is associated with the first channel (205). A second gate ((220) – near (203)) is associated with the second channel (203). A capacitor (282, 284) is coupled with the first source/drain (206). A digit line (172) is beneath the pillar and is electrically coupled with the third source/drain (202).
For the DRAM memory cell in fig. 3, Lee does not explicitly disclose that the first gate ((220) – near (205)) and the second gate ((220) – near (203)) are electrically coupled to a single logical access line/word line. However Zheng discloses that using a single word line provides the benefit of saving layout space (p. 2-3, paragraph 25). Lee discloses that high density memory devices are desirable in the art (p. 1, paragraphs 23-24). In view of the above, it would therefore be obvious to electrically couple the first gate ((220) – near (205)) and the second gate ((220) – near (203)) to a single logical access line/word line.
Lee does not explicitly disclose first and second physical access lines that respectively connect the first gate ((220) – near (205)) and the second gate ((220) – near (203)) to a common word line. However Ding discloses the known use of physical access lines in the form of contact plugs to establish electrical contact to a word line (column 3, lines 21-24). It would be obvious to implement physical access lines in the form of contact plugs in order to establish electrical contact to a word line since choosing from a finite number of identified, predictable solutions ("obvious to try") with a reasonable expectation of success have been found to be obvious. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). Thus claim 9 is not patentable over the above cited references.
With regard to claim 10, in the device of Lee constructed in view of Zheng and Ding, the first and second transistors are both coupled to a single logical access line in the form of a common word line. Fig.3 of Lee shows a first transistor is associated with the first gate ((220) – near (205)), the first source/drain (206), and the second source/drain (204) and a second transistor is associated with the second gate ((220) – near (203)), the second source/drain (204), the third source/drain (202). In the device of Lee constructed in view of Zheng and Ding, the first and second transistors are both coupled to a single logical access line in the form of a common word line.
In reference to claim 11, in the device of Lee constructed in view of Zheng and Ding, the first and second transistors are both coupled to a single logical access line in the form of a common word line. In fig. 3 of Lee, turning on the transistors through the first gate ((220) – near (205)) and the second gate ((220) – near (203)) selectively couples the capacitor (282, 284) and the digit line (172).
With regard to claim 12, the first gate ((220) – near (205)) controls a flow of current through a first portion (205) of the pillar while the second gate ((220) – near (203)) controls a flow of current through a second portion (203) of the pillar.
In reference to claim 13, a first vertical surface faces the first gate ((220) – near (205)) and a second vertical surface faces the second gate ((220) – near (203)).
With regard to claim 14, Lee discloses (p. 3, paragraph 67) that the first gate ((220) – near (205)) is isolated from the first channel (205) by a first dielectric while the second gate ((220) – near (203)) is isolated from the second channel (203) by a second dielectric.
In reference to claim 15, Lee discloses a similar device. Figure 3 of Lee discloses a memory device in the form of a DRAM memory cell with a plurality of memory cells that each includes a pillar comprising a first source/drain (206), a second source/drain (204), a third source/drain (202), a first channel (205) between the first source/drain (206) and the second source/drain (204), and a second channel (203) between the second source/drain (204) and the third source/drain (202). A first gate ((220) – near (205)) is associated with the first channel (205). A second gate ((220) – near (203)) is associated with the second channel (203). A capacitor (282, 284) is coupled with the first source/drain (206).
For the DRAM memory cell in fig. 3, Lee does not explicitly disclose that the first gate ((220) – near (205)) and the second gate ((220) – near (203)) are electrically coupled to a single logical access line/word line. However Zheng discloses that using a single word line provides the benefit of saving layout space (p. 2-3, paragraph 25). Lee discloses that high density memory devices are desirable in the art (p. 1, paragraphs 23-24). In view of the above, it would therefore be obvious to electrically couple the first gate ((220) – near (205)) and the second gate ((220) – near (203)) to a single logical access line/word line.
Lee does not explicitly disclose first and second physical access lines that respectively connect the first gate ((220) – near (205)) and the second gate ((220) – near (203)) to a common word line. However Ding discloses the known use of physical access lines in the form of contact plugs to establish electrical contact to a word line (column 3, lines 21-24). It would be obvious to implement physical access lines in the form of contact plugs in order to establish electrical contact to a word line since choosing from a finite number of identified, predictable solutions ("obvious to try") with a reasonable expectation of success have been found to be obvious. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). Thus claim 15 is not patentable over the above cited references.
With regard to claim 16, the first gate ((220) – near (205)) is positioned on a first side of the pillar at a first height while the second gate ((220) – near (203)) is positioned on a second side of the pillar at a second height.
In reference to claim 17, the first height is associated with controlling a flow of current through the first channel (205) of the pillar while the second height is associated with controlling a flow of current through the second channel (203).
With regard to claim 18, fig. 3 of Lee shows a digit line (172) is beneath the pillar; it is understood that there is plurality of digit lines (172) coupled to a plurality of memory cell pillars. In fig. 3 of Lee, turning on the transistors through the first gate ((220) – near (205)) and the second gate ((220) – near (203)) selectively couples the capacitor (282, 284) and the digit line (172).
In reference to claim 19, the capacitor (282, 284) is electrically isolated from the digit line (172) when one or more of the first gate ((220) – near (205)) and the second gate ((220) – near (203)) is deactivated.
With regard to claim 20, Lee discloses (p. 3, paragraph 67) that the first gate ((220) – near (205)) is separated from the first channel (205) the second channel (203) by a first dielectric while the second gate ((220) – near (203)) is separated from the second channel (203) or the first channel (205) by a second dielectric.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-4 and 6-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-5, 9-11, 13, 14, 16, 18, 19, and 21 of U.S. Patent No. 12,004,338 B2 (hereinafter “Servalli”). Although the claims at issue are not identical, they are not patentably distinct from each other because species claims 1-5, 9-11, 13, 14, 16, 18, 19, and 21 of Servalli anticipate genus claims 1-4 and 6-20.
In reference to claim 1, species claim 1 of Servalli anticipates genus claim 1 of the currently filed application. Species claim 1 of Servalli describes first, second, third, and fourth gates proximate to channels in a pillar which anticipate first, second, third, and fourth gates proximate to channels in claim 1. The upper and lower channels of species claim 1 of Servalli anticipate the first and second channels of claim 1. The upper, middle, and lower source/drain of Servalli anticipate the first, second, and third source/drain of claim 1. Both species claim 1 of Servalli and claim 1 of the currently filed application describe a digit line that is coupled to a source/drain region. As noted above, lower third source/drain of species claim 1 of Servalli corresponds to the third source/drain of claim 1.
With regard to claim 2, claim 1 of Servalli describes the electrical contact region while claim 4 of Servalli describes the capacitor. As noted above, upper source/drain of species claim 1 of Servalli corresponds to the first source/drain of claim 2 of the currently filed application.
In reference to claim 3, claim 5 of Servalli anticipates claim 3. As noted above, the upper, middle, and lower source/drain of species claim 1 of Servalli anticipate the first, second, and third source/drain of claim 3 of the currently filed application.
With regard to claim 4, claim 5 of Servalli anticipates claim 4. Species claim 5 of Servalli and claim 4 of the currently filed application both describe the transistors having their dedicated gates and source/drain regions.
In reference to claim 6, the nearly identical language of species claim 2 of Servalli anticipates claim 6 of the currently filed application. The only difference in currently filed claim 6 is that the term, “coupled,” is used which is anticipated by “electrically coupled,” in species claim 2 of Servalli.
With regard to claim 7, the nearly identical language of species claim 3 of Servalli anticipates claim 7 of the currently filed application. The only difference in claim 7 of the currently filed application is that the term, “not coupled,” is used which is anticipated by “not electrically coupled” in species claim 3 of Servalli.
In reference to claim 8, species claim 1 of Servalli anticipates claim 8 of the currently filed application since it recites first and second gates which face a left-facing vertical surface that faces a first direction. Species claim 1 of Servalli also recites third and fourth gates which face a right-facing vertical surface that faces a second direction.
In reference to claim 9, species claim 9 of Servalli anticipates claim 9 of the currently filed application. Species claim 9 of Servalli describes first, second, third, and fourth gates proximate to channels in a pillar which anticipate first, second, third, and fourth gates proximate to channels in claim 9. The upper and lower channels of species claim 9 of Servalli anticipate the first and second channels of claim 9. The upper, middle, and lower source/drain of Servalli anticipate the first, second, and third source/drain of claim 9. Both species claim 9 of Servalli and claim 9 of the currently filed application describe a digit line that is coupled to a source/drain region. As noted above, lower third source/drain of species claim 9 of Servalli corresponds to the third source/drain of claim 9.
With regard to claim 10, species claim 10 of Servalli anticipates claim 10 of the currently filed application since it uses almost the exact same language.
With regard to claim 11, species claim 10 of Servalli anticipates claim 11 of the currently filed application since they both claim a single logical access line that couples the capacitor and the digit line.
In reference to claim 12, species claim 11 of Servalli anticipates claim 12 of the currently filed application since it uses almost the exact same language.
In reference to claim 13, species claim 9 of Servalli anticipates claim 13 of the currently filed application since it uses almost the exact same language.
With regard to claim 14, species claim 13 of Servalli anticipates claim 14 of the currently filed application since it uses almost the exact same language.
In reference to claim 15, species claim 14 of Servalli anticipates claim 15 of the currently filed application. Species claim 14 of Servalli describes first and second gates respectively coupled to first and second physical access lines that are electrically coupled to form a single logical access line. The upper and lower channels of species claim 14 of Servalli anticipate the first and second channels of claim 15. The upper, middle, and lower source/drain of Servalli anticipate the first, second, and third source/drain of claim 15. Both species claim 14 of Servalli and claim 15 of the currently filed application describe a capacitor that is coupled to a source/drain region. As noted above, upper third source/drain of species claim 15 of Servalli corresponds to the first source/drain of claim 15.
With regard to claim 16, species claim 14 of Servalli anticipates claim 16 of the currently filed application since it uses almost the exact same language.
In reference to claim 17, species claim 16 of Servalli anticipates claim 17 of the currently filed application since it uses almost the exact same language.
With regard to claim 18, species claim 19 of Servalli anticipates claim 18 of the currently filed application since it uses almost the exact same language.
In reference to claim 19, species claim 21 of Servalli anticipates claim 19 of the currently filed application since it uses almost the exact same language.
With regard to claim 20, species claim 18 of Servalli anticipates claim 20 of the currently filed application since it uses almost the exact same language.
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: in the examiner’s opinion, it would not be obvious to implement an integrated assembly that comprises a pillar structure with the suggested multiple source/drain regions, first and second channels, in combination with the specific first, second, third, and fourth gate structures that form diagonally opposed pairs as described by the applicant in claim 5.
Conclusion
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/KEVIN QUINTO/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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