DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant election without traverse of Invention I (claims 1-9) in the reply filed on 8.17.2026 is acknowledged.
The examiner contacted the applicant on 8.26.2026 to inform them of a missing election of species of the previous Office Action. Mr. Sangki Park, Reg. No. 77,261, elected without traverse Species A (Fig. 1A) and Species F (Fig. 3A) with claims 1 -9 being readable on the elected species.
Claims 10-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected inventions, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 8.17.2026.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “inner surface” and a separate “side surface” both of the “connection structure” of claim 1 (note: per the indefiniteness rejection below it appears these surfaces refer to a same/common surface and not different ones) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, “a connection structure arranged on the package substrate and comprising an inner surface that surrounds a sidewall of the semiconductor chip” (emphasis added) and “a sealant covering an upper surface of the semiconductor chip that faces the metal plate and in contact with a side surface of the connection structure” (emphasis added) renders the claim indefinite because it appears to be using two different terms (“inner surface” and “side surface”) to refer to a common surface of the connection structure; using different terms to refer to the same element obscures the scope of the claim.
The specification does not aid in resolving this inconsistency since the term “inner surface” is only found in claim 1 which the examiner takes it as support that “inner surface” and “side surface” of the connection structure are referring to the same surface; the examiner examines it as such or as presented.
None of the dependent claims 2-9 address this deficiency and are rejected along with base claim 1.
Examiner Note
Multiple prior art rejections are applied to the claims to show unpatentability of the claims based on different interpretations and/or the breadth of the claims.
Claim Rejections - 35 USC § 102 and 35 USC § 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Long et al. (US 5175612 A).
Regarding claim 1, Long discloses a semiconductor device (Fig. 2) comprising:
a package substrate (48 and layers below);
a semiconductor chip (52) stacked on the package substrate along a vertical direction;
a connection structure (56+60) arranged on the package substrate and comprising an inner surface (innermost of 56) that surrounds a sidewall of the semiconductor chip;
a metal plate (70 or parts thereof) attached (indirectly attached which is not precluded by the claim) to the inner surface of the connection structure; and
a sealant (58) covering an upper surface of the semiconductor chip that faces the metal plate and in contact with a (inner) side surface (abutting 58) of the connection structure (56+60).
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Regarding claim 3, Long discloses the semiconductor device of claim 1, wherein each (inner) side surface (limited to the slated surface) of the connection structure (56+60) does not overlap a side surface of the semiconductor chip (52) in the vertical direction (Fig. 2).
Regarding claim 4, Long discloses the semiconductor device of claim 1, wherein a lower (most) surface of the metal plate (70 or parts thereof) is arranged at a vertical level higher than the upper surface of the semiconductor chip (52, Fig. 2).
Regarding claim 7, Long discloses the semiconductor device of claim 1, wherein the sealant (58) is formed to fill (partly) between the semiconductor chip and the metal plate (note that 58 is placed above 52) in an internal space defined by the connection structure (56+60, Fig. 2).
Claims 1 and 3-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oku (JP H09246433 A, machine translation provided).
Regarding claim 1, Oku discloses a semiconductor device (Figs. 1-2; annotated below) comprising:
a package substrate (1);
a semiconductor chip (2) stacked on the package substrate along a vertical direction;
a connection structure (4 or 11) arranged on the package substrate and comprising an inner surface (upper surface contacting 5) that surrounds a sidewall of the semiconductor chip;
a metal plate (5) attached to the inner surface of the connection structure; and
a sealant (7) covering an upper surface of the semiconductor chip that faces the metal plate and in contact with a side surface (lower surface) of the connection structure.
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Regarding claim 3, Oku discloses the semiconductor device of claim 1, wherein each side surface (Figs. 1-2) of the connection structure (4 or 11) does not overlap a side surface of the semiconductor chip (2) in the vertical direction (Figs. 1-2).
Regarding claim 4, Oku discloses the semiconductor device of claim 1, wherein a lower (most) surface of the metal plate (5) is arranged at a vertical level higher than the upper surface of the semiconductor chip (2, Figs. 1-2).
Regarding claim 5, Oku discloses the semiconductor device of claim 1, wherein an internal space defined by the connection structure (4 or 11) surrounding the semiconductor chip (2) has a rectangular shape in a plan view (Figs. 1-2).
Regarding claim 6, Oku discloses the semiconductor device of claim 5, wherein a horizontal (total) area of the rectangular shape (defined by 4 or 11) is greater than a horizontal (total) area of the semiconductor chip (2, Figs. 1-2).
Regarding claim 7, Oku discloses the semiconductor device of claim 1, wherein the sealant (7) is formed to fill between the semiconductor chip (2) and the metal plate (5) in an internal space defined by the connection structure (4 or 11, Figs. 1-2).
Claims 2 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Oku (JP H09246433 A, machine translation provided).
Regarding claims 2 and 8, Oku fails to disclose (claim 2) the semiconductor device of claim 1, wherein the metal plate comprises copper and (claim 8) the semiconductor device of claim 1, wherein the sealant comprises an epoxy molding compound.
Copper is a well-known and commonly used material in heat dissipation structures due to its thermal conductivity.
Epoxy molding compound is a well-known and commonly used material in encapsulating chips due to its flowability, coverage and/or ability to protect chips.
It would have been obvious, before the effective filing date, to one of ordinary skill in the art to include the materials claimed in claims 2 and 8 in the device of Oku because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07), so as to (claim 2) provide a material with a high thermal conductivity and so as to (claim 8) fully encapsulate the semiconductor chip.
Claims 1-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mertol et al. (US 5940271 A).
Regarding claim 1, Mertol discloses a semiconductor device (Figs. 7B-8) comprising:
a package substrate (2);
a semiconductor chip (1) stacked on the package substrate along a vertical direction;
a connection structure (11) arranged on the package substrate and comprising an inner (top) surface that surrounds a sidewall of the semiconductor chip (Figs. 4A and 5A);
a metal plate (8) attached to the inner surface of the connection structure; and
a sealant covering (6) an upper surface of the semiconductor chip that faces the metal plate and in contact with a side (lower) surface of the connection structure.
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Regarding claim 2, Mertol discloses the semiconductor device of claim 1, wherein the metal plate (“heat sink 8”) comprises copper (“Embodiments of the heat sink are formed with powdered metal or thermally-conductive material such as aluminum, copper, copper/tungsten, plastic or any other known material”).
Regarding claim 3, Mertol discloses the semiconductor device of claim 1, wherein each side (lower) surface of the connection structure (11) does not overlap a side surface of the semiconductor chip (1) in the vertical direction (Figs. 7B-8).
Regarding claim 4, Mertol discloses the semiconductor device of claim 1, wherein a lower surface of the metal plate (8) is arranged at a vertical level higher than the upper surface of the semiconductor chip (1, Figs. 7B-8).
Regarding claim 5, Mertol discloses the semiconductor device of claim 1, wherein an internal space defined by the connection structure (11) surrounding the semiconductor chip has a rectangular (a square is a rectangle) shape in a plan view (Figs. 4A and 5A).
Regarding claim 6, Mertol discloses the semiconductor device of claim 5, wherein a horizontal area of the rectangular (square) shape is greater than a horizontal area of the semiconductor chip (Figs. 4A, 5A and 7B-8).
Regarding claim 7, Mertol discloses the semiconductor device of claim 1, wherein the sealant (6) is formed to fill between the semiconductor chip (1) and the metal plate (8) in an internal space defined by the connection structure (11, Figs. 7B-8).
Regarding claim 8, Mertol discloses the semiconductor device of claim 1, wherein the sealant (“encapsulant 6”) comprises an epoxy molding compound (“suitable encapsulant is found in an epoxy”).
Claims 1 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chi et al. (US 20210118767 A1).
Regarding claim 1, Chi discloses a semiconductor device (Fig. 1D) comprising:
a package substrate (110);
a semiconductor chip (120) stacked on the package substrate along a vertical direction;
a connection structure (160) arranged on the package substrate and comprising an inner (top) surface that surrounds (Fig. 1C-1) a sidewall of the semiconductor chip;
a metal plate (190) attached (indirectly via 180) to the inner surface of the connection structure; and
a sealant (140+180; MPEP 2111) covering (indirectly and in a diagonal direction) an upper surface of the semiconductor chip that faces the metal plate and in contact with a side (lower) surface of the connection structure.
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Regarding claim 9, Chi discloses the semiconductor device of claim 1, further comprising chip connection bumps (130) between a chip pad (bottom) of the semiconductor chip and the package substrate (110),
wherein the sealant (140+180; MPEP 2111) is between the semiconductor chip and the package substrate and is in contact with the chip connection bumps (Fig. 1D).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 5891753 A to Akram discloses a connection structure (428), a shield plate (422) connected to the connection structure and a semiconductor chip (402) surrounded by the connect structure and covered by the shield plate (Fig. 4).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andres Munoz/ Primary Examiner, Art Unit 2818
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