Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II, species C, corresponding to Claims 15-20 in the reply filed on 08/13/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 15 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by LIM (Pub. No.: US 2022/0382687).
Re claim 15, LIM, FIG. 13 teaches a packaging structure of a multi-layer stacked memory, comprising:
a buffer chip (BASE DIE); and
a plurality of micro-memory modules (412),
wherein:
the buffer chip is provided with a plurality of first conductive vias (TSV); and
the plurality of micro-memory modules (412) are sequentially stacked on the buffer chip, and an orthographic projection of the micro-memory modules on the buffer chip coincides with the buffer chip (BASE DIE).
Claim(s) 15-20 is/are rejected under 35 U.S.C. 102(a)(1)/(2) as being anticipated by Wilkerson (Pub. No.: US 2020/0194413).
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Re claim 15, Wilkerson, FIG. 11 teaches a packaging structure of a multi-layer stacked memory, comprising:
a buffer chip (1202, [0034]); and
a plurality of micro-memory modules (1204/1208/1212/1216),
wherein:
the buffer chip is provided with a plurality of first conductive vias (1222); and
the plurality of micro-memory modules (1204/1208/1212/1216) are sequentially stacked on the buffer chip, and an orthographic projection of the micro-memory modules on the buffer chip coincides with the buffer chip (1202).
Re claim 16, Wilkerson, FIG. 11 teaches the packaging structure according to claim 15, wherein:
each of the micro-memory modules (1204/1208/1212/1216) includes a dummy chip and a first memory chip;
the dummy chip [FDC] is provided with a groove body;
the groove body is provided with a first memory chip (1206); and
the first memory chip is provided with a plurality of second conductive vias (the two 1222 on the left) corresponding to and electrically connected to the plurality of first conductive vias (1222).
Re claim 17, Wilkerson, FIG. 11 teaches the packaging structure according to claim 15, wherein:
each of the plurality of micro-memory modules (1204/1208/1212/1216) includes a dummy chip [FDC] and a stacked memory module;
the dummy chip [FDC] is provided with a groove body;
the groove body is provided with the stacked memory module;
the stacked memory module includes a plurality of first memory chips (1206/1210/1214) stacked in sequence;
first memory chips (1206/1210/1214) in every two adjacent layers are hybrid-bonded; and
the first memory chips are provided with a plurality of second conductive (the two 1222 on the left) vias corresponding to and electrically connected to the plurality of first conductive vias (1222).
Re claim 18, Wilkerson, FIG. 1 teaches the packaging structure according to claim 15, further comprising:
a second micro-memory module (left (1204/1208/1212/1216)),
wherein:
the buffer chip (1202) is provided with a plurality of first conductive vias;
the second micro-memory module (left (1204/1208/1212/1216)) is hybrid-bonded and stacked on the buffer chip, the plurality of first micro-memory modules are hybrid-bonded and stacked on the second micro-memory module and an orthographic projection of the first micro-memory modules (right (1204/1208/1212/1216)) and the second micro-memory module on the buffer chip coincides with the buffer chip;
each of the plurality of first micro-memory modules includes a first memory chip and a dummy chip [FDC] provided with a first groove body and a plurality of first cooling vias;
the first groove body (filled with 1222) is provided with a first memory chip;
the first memory chip is provided with a plurality of second conductive vias (the two 1222 on the left) corresponding to and electrically connected to the plurality of first conducive vias (1222);
the second micro-memory module (left (1204/1208/1212/1216)) includes a first memory chip, a second dummy chip, and a third dummy chip sandwiched between the first dummy chip and the second dummy chip;
the second dummy chip and the third dummy chip [TDC] are provided with a second groove body [SGB] corresponding to the first groove body [FGB];
the second groove body is provided with the first memory chip (1206); and
the third dummy chip is provided with a second cooling via (1222 form within [TDC] corresponding to and connected to the first cooling via.
Re claim 19, Wilkerson, FIG. 1 teaches the packaging structure according to claim 15, further comprising:
a dummy chip [FDC];
a first memory chip (right 1204);
a plastic encapsulation layer (top-most layer of FIG. 12); and
a plurality of second memory chips (left 1204),
wherein:
the plurality of second memory chips are stacked on the buffer chip (1202);
the first memory chip (right 1204) is disposed on a side of the plurality of second memory chips (left 1204) facing away from the buffer chip;
the dummy chip [FDC] is bonded and connected to a side of the first memory chip facing away from the buffer chip through a bonding structure;
the plastic encapsulation layer wraps the dummy chip, the buffer chip, the first memory chip and the plurality of second memory chips; and,
the dummy chip is provided with a plurality of first heat dissipation vias (right 1222 formed within [FDC]), and the buffer chip, the first memory chip and the plurality of second memory chips are all provided with a plurality of second heat dissipation vias (left 1222 formed within [FDC]) corresponding to the plurality of first heat dissipation vias, and
the plurality of second memory chips (1208) and the buffer chip are further provided with a plurality of conductive vias.
Re claim 20, Wilkerson, FIG. 1 teaches the packaging structure according to claim 19, wherein:
the buffer chip includes a substrate (1202);
wherein:
the plurality of second memory chips (left 1204/1208/1212/1216) are sequentially stacked on the substrate;
the first memory chip (right 1204/1208/1212/1216) is disposed on a side of the plurality of second memory chips facing away from the substrate;
the dummy chip [FDC] is disposed on a side of the first memory chip facing away from the substate and thermal compression bonded with the first memory chip;
the plastic encapsulation layer (top-most layer of FGI. 12) wraps the dummy chip, the substrate, the first memory chip and the plurality of second memory chips; and,
the first memory chip and the plurality of second memory chips are all provided with a plurality of first heat dissipation vias (1222 formed within), the dummy chip is provided with a plurality of second heat dissipation vias corresponding to the plurality of first heat dissipation vias, and the plurality of second memory chips are provided with a plurality of conductive vias.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TONY TRAN/Primary Examiner, Art Unit 2893
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