DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 6, 9, 12, 14 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites “the support structure comprises a plurality of support structures supporting the first overhang in at least one region between the substrate and the first overhang”. It is not clear what is meant by “the support structure comprises a plurality of support structures supporting the first overhang” in the above context, given that no shape or size or other geometry of “support structure” is recited. As such, any support that is made of more than one part may be considered a comprising “a plurality of support structures”. Given that para 68 describes “support structure 300 may include upper pads 310, an insulating body 320, lower pads 330, and conductive pillars 340”, support structure 300 reads on “the support structure comprises a plurality of support structures supporting the first overhang”. Claims 6, 9, 12, 14 and 17 also recite “the support structure comprises a plurality of support structures” and will be interpreted similarly.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 20 is rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Yoon (US 20130277831), hereinafter Yoon.
Regarding claim 20, Yoon teaches a method of forming a multichip package (refer to Figured 12A-B; alternatively refer to Figure 4) comprising:
preparing a substrate (100– see para 179) connected to a plurality of solder balls (170– see para 54, shown in Figure 12B but not labelled, labelled in Figure 11);
forming a support structure (comprising 300, 410 - see para 68 and 92) over the substrate (100), wherein the support structure is connected (at least mechanically) to an external electrical connection (170 form “external terminals” – see para 54) for the substrate (100);
stacking a first chip (200A – see para 179) over the substrate (100); and
stacking a second chip (200B – see para 179) stacked over the first chip and the support structure, wherein an overhang (part of 200B that comprises 210B – see figure 12B) of the second chip (200B) is not supported by the first chip (best seen in figure 12B); and is supported by the support structure (300).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10, 12-19 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon.
Regarding claim 1, Yoon teaches a multichip package (refer to Figured 12A-B; alternatively refer to Figure 4) comprising:
a substrate (100– see para 179) connected to a plurality of solder balls (170– see para 54, shown in Figure 12B but not labelled, labelled in Figure 11) including a first solder ball (one of 170);
a first chip (200A – see para 179) stacked over the substrate (100);
a second chip (200B – see para 179) stacked over the first chip (200A) and including a first overhang (part of 200B that comprises 210B – see figure 12B) not supported by the first chip (best seen in figure 12B); and
a support structure (comprising 300, 410 - see para 68 and 92) supporting the first overhang and the first solder ball acts as external terminals to the substrate (para 47).
Yoon does not specifically state that the first solder ball provides “an external electrical connection to the substrate for a voltage external to the substrate”. However, Yoon teaches that the pads of substrate (100) may be configured to transmit power voltage to the first chip (200A), second chip (200B) and other chips (para 184). It would have been obvious to one of ordinary skills in the art before the effective filing of the claimed invention to modify Yoon so that the first solder ball provides an external electrical connection to the substrate for a voltage external to the substrate. The ordinary artisan would have been motivated to modify Yoon for at least the purpose of using the external terminals to connect to the pads (190) to an external voltage source, thus using an electrical connection to the substrate to power the first chip, and powering the multichip package.
Regarding claim 2, Yoon (refer to Figured 12A-B) teaches the multichip package of claim 1, but does not specifically state that “the external electrical connection provides access to a ground voltage and a voltage different from the ground voltage”. However, Yoon teaches that the pads of substrate (100) may be configured to transmit power voltage or a ground voltage to the first chip (200A), second chip (200B) and other chips (para 184). It would have been obvious to one of ordinary skills in the art before the effective filing of the claimed invention to modify Yoon so that the external electrical connection provides access to a ground voltage and a voltage different from the ground voltage. The ordinary artisan would have been motivated to modify Yoon for at least the purpose of using the external terminals to connect not only an external voltage but also a ground to electrically operate the first chip, and the multichip package.
Regarding claim 3, Yoon (refer to Figured 12A-B) teaches the multichip package of claim 5, wherein the support structure (comprising 300, 410) comprises a plurality of support structures (300 comprises 310, 320 and multiple 340 – see Figure 12B; also see 35 USC 112, 2nd paragraph rejection above) supporting the first overhang (part of 200B that comprises 210B – see figure 12B) in at least one region (i.e. region where 410 contacts 200B – see Figure 12B) between the substrate (100) and the first overhang.
Regarding claim 4, Yoon (refer to Figured 12A-B) teaches the multichip package of claim 1, further comprising a third chip (200C) stacked over the second chip (200B) and including a second overhang (part of 200C that comprising 210C – see figure 12B) not supported by the second chip (200B).
Regarding claim 5, Yoon (refer to Figured 12A-B) teaches the multichip package of claim 4, wherein the support structure (comprising 300, 410) supports the second overhang (best seen in Figure 12B).
Regarding claim 6, Yoon (refer to Figured 12A-B) teaches the multichip package of claim 5, wherein the support structure (comprising 300, 410) comprises a plurality of support structures (300 comprises 310, 320 and multiple 340 – see Figure 12B; also see 35 USC 112, 2nd paragraph rejection above) supporting the second overhang (part of 200C that comprises 210C – see figure 12B) in at least one region (i.e. region where 410 contacts 200C – see Figure 12B) between the substrate (100) and the second overhang.
Regarding claim 7, Yoon (refer to Figured 12A-B) teaches the multichip package of claim 4, further comprising a fourth chip (200D) stacked over the third chip (200C) and including a third overhang (part of 200D that comprises 210D – see figure 12B) not supported by the third chip (200C).
Regarding claim 8, Yoon (refer to Figured 12A-B) teaches the multichip package of claim 7, wherein the support structure (comprising 300, 410) supports at least one (see Figure 12B) of the second overhang (part of 200C that comprises 210C – see figure 12B) and the third overhang (part of 200D that comprises 210D – see figure 12B).
Regarding claim 9, Yoon (refer to Figured 12A-B) teaches the multichip package of claim 5, wherein the support structure (comprising 300, 410) comprises a plurality of support structures (300 comprises 310, 320 and multiple 340 – see Figure 12B; also see 35 USC 112, 2nd paragraph rejection above) supporting the third overhang (part of 200D that comprises 210D – see figure 12B) in at least one region (i.e. region where 410 contacts 200D – see Figure 12B) between the substrate (100) and the third overhang.
Regarding claim 10, Yoon teaches a multichip package (refer to Figured 12A-B) comprising:
a substrate (100– see para 179) connected to a plurality of solder balls (170– see para 54, shown in Figure 12B but not labelled, labelled in Figure 11) including a first solder ball (a one of 170);
a first chip (200A – see para 179) stacked over the substrate (100);
a second chip (200B – see para 179) stacked over the first chip and including a first overhang not supported by the first chip (best seen in figure 12B); and
a support structure (comprising 300, 410 - see para 68 and 92) supporting the first overhang and connected (at least mechanically) to the first solder ball (the one of 170)
Yoon does not show all electrical connections of 170 to other parts of the circuit, and although it teaches provision of a ground (para 184), Yoon does not teach that the first solder ball (the one of 170) provides for of the multichip package “an external electrical connection for a device external to the substrate”. However, Yoon teaches that the pads of substrate (100) may be configured to transmit power voltage or a ground voltage to the first chip (200A), second chip (200B) and other chips (para 184). It would have been obvious to one of ordinary skills in the art before the effective filing of the claimed invention to modify Yoon so that the first solder ball provides for of the multichip package “an external electrical connection for a device external to the substrate. The ordinary artisan would have been motivated to modify Yoon for at least the purpose of electrically connecting to a device external to the substrate, with the external device providing voltage and ground required to operate the multichip package.
Regarding claim 12, Yoon (refer to Figured 12A-B) teaches the multichip package of claim 10, wherein the support structure (comprising 300, 410) comprises a plurality of support structures (300 comprises 310, 320 and multiple 340 – see Figure 12B; also see 35 USC 112, 2nd paragraph rejection above) supporting the first overhang (part of 200B that comprises 210B – see figure 12B) in at least one region (i.e. region where 410 contacts 200B – see Figure 12B) between the substrate (100) and the first overhang.
Regarding claim 13, Yoon (refer to Figured 12A-B) teaches the multichip package of claim 10, further comprising a third chip (200C) stacked over the second chip (200B) and including a second overhang (part of 200C that comprising 210C – see figure 12B) not supported by the second chip (200B), wherein the support structure (comprising 300, 410) supports the second overhang (best seen in Figure 12B).
Regarding claim 14, Yoon (refer to Figured 12A-B) teaches the multichip package of claim 10, wherein the support structure (comprising 300, 410) comprises a plurality of support structures (300 comprises 310, 320 and multiple 340 – see Figure 12B; also see 35 USC 112, 2nd paragraph rejection above) supporting the second overhang (part of 200C that comprises 210C – see figure 12B) in at least one region (i.e. region where 410 contacts 200C – see Figure 12B) between the substrate (100) and the second overhang
Regarding claim 15, Yoon (refer to Figured 12A-B) teaches the multichip package of claim 10, further comprising a third chip (200C) stacked over the second chip (200B) and including a second overhang (part of 200C that comprising 210C – see figure 12B) not supported by the second chip (200B).
; and a fourth chip (200D) stacked over the third chip (200C) and including a third overhang (part of 200D that comprises 210D – see figure 12B) not supported by the third chip (200C).
Regarding claim 16, Yoon (refer to Figured 12A-B) teaches the multichip package of claim 15, wherein the support structure (comprising 300, 410) supports at least one (see Figure 12B) of the second overhang (part of 200C that comprises 210C – see figure 12B) and the third overhang (part of 200D that comprises 210D – see figure 12B).
Regarding claim 17, Yoon (refer to Figured 12A-B) teaches the multichip package of claim 16, wherein the support structure (comprising 300, 410) comprises a plurality of support structures (300 comprises 310, 320 and multiple 340 – see Figure 12B; also see 35 USC 112, 2nd paragraph rejection above) supporting the second overhang (part of 200C that comprises 210C – see figure 12B) in at least one region between the substrate (100) and the second overhang (part of 200C that comprises 210C – see figure 12B) and the third overhang (part of 200D that comprises 210D – see figure 12B) in at least one region between the substrate (100) and the third overhang (part of 200D that comprises 210D – see figure 12B).
Regarding claim 18, Yoon teaches a multichip package (refer to Figured 12A-B; alternatively refer to Figure 4) comprising:
a substrate (100– see para 179) connected to a plurality of solder balls (170– see para 54, shown in Figure 12B but not labelled, labelled in Figure 11) including a first solder ball (one of 170) and a second solder ball (another one of 170);
a first chip (200A – see para 179) stacked over the substrate (100);
a second chip (200B – see para 179) stacked over the first chip and including a first overhang (part of 200B that comprises 210B – see figure 12B) not supported by the first chip (best seen in figure 12B);
a third chip (200C) stacked over the second chip (200B) and including a second overhang (part of 200C comprising 210C – see figure 12B) not supported by the second chip (200B);
a first support structure (comprising 301 of 300) supporting the first overhang and connected to (at least mechanically) the first solder ball; and
a second support structure (comprising 302 of 300) supporting the second overhang (part of 200C that comprising 210C – see figure 12B) and connected to (at least mechanically) the second solder ball.
Yoon does not clearly teach electrical path to 170 and as such does not teach that the first solder ball “provides a first external electrical connection for the substrate” that the second solder ball provides “a second external electrical connection for the substrate”. However, Yoon teaches that the pads of substrate (100) may be configured to transmit power voltage to the first chip (200A), second chip (200B) and other chips (para 184). It would have been obvious to one of ordinary skills in the art before the effective filing of the claimed invention to modify Yoon so that the solder balls provide the external electrical connection for power and ground such that the first solder ball “provides a first external electrical connection for the substrate” that the second solder ball provides “a second external electrical connection for the substrate”. The ordinary artisan would have been motivated to modify Yoon for at least the purpose of using the external terminals to connect to the pads (190) to an external voltage source, thus using an electrical connection to the substrate to power the multiple chips of the multichip package.
Regarding claim 19, Yoon (US 20130277831) teaches a multichip package (refer to Figured 12A-B; alternatively refer to Figure 4) comprising:
a substrate (100– see para 179) connected to a plurality of solder balls (170– see para 54, shown in Figure 12B but not labelled, labelled in Figure 11) including a first solder ball (one of 170) and a second solder ball (another one of 170);
a first chip (200A – see para 179) stacked over the substrate (100);
a second chip (200B – see para 179) stacked over the first chip and including a first overhang (part of 200B that comprises 210B – see figure 12B) not supported by the first chip (best seen in figure 12B);
a third chip (200C) stacked over the second chip (200B) and including a second overhang (part of 200C that comprises 210C – see figure 12B) not supported by the second chip (200B);
a fourth chip (200C) stacked over the third chip (200C) and including a third overhang (part of 200D that comprises 210D – see figure 12B) not supported by the third chip (200C);
a first support structure (comprising 301 of 300) supporting the first overhang and connected to (at least mechanically) the first solder ball; and
a second support structure (comprising 302 of 300) supporting the second overhang (part of 200C that comprising 210C – see figure 12B) and connected to (at least mechanically) the second solder ball.
Yoon does not clearly teach electrical path to 170 and as such does not teach that the first solder ball “provides a first external electrical connection for the substrate for a first voltage” and that the second solder ball provides “a second external electrical connection for the substrate for a second voltage”. However, Yoon teaches that the pads of substrate (100) may be configured to transmit power voltage and ground voltage to the first chip (200A), second chip (200B) and other chips (para 184). It would have been obvious to one of ordinary skills in the art before the effective filing of the claimed invention to modify Yoon so that the solder balls provide the external electrical connection for power and ground such that that the first solder ball “provides a first external electrical connection for the substrate for a first voltage” and that the second solder ball provides “a second external electrical connection for the substrate for a second voltage”. The ordinary artisan would have been motivated to modify Yoon for at least the purpose of using the external terminals to connect to the pads (190) to an external voltage source providing a first and a second voltage, such as power and ground, thus using an electrical connection to the substrate to power the multiple chips of the multichip package.
Regarding claim 21, Yoon teaches a multichip package (refer to Figured 12A-B; alternatively refer to Figure 4) comprising:
a substrate (100– see para 179);
a first chip (200A – see para 179) stacked over the substrate (100);
a second chip (200B – see para 179) stacked over the first chip (200A), wherein the second chip is offset from the first chip in a first direction (i.e. horizontal direction in orientation of Figure 12A-B or 4) resulting in an overhang (part of 200B that comprises 210B – see figure 12B); and
a support structure (comprising 300, 410 - see para 68 and 92) disposed between the overhang and the substrate and connected to an external electrical connection (provided by 170 – see para 54) for the substrate.
Yoon does not specifically state that the support structure is “electrically” connected to the external electrical connection (170) for the substrate. However, Yoon teaches that the pads of substrate (100) may be configured to transmit power voltage to the first chip (200A), second chip (200B) and other chips (para 184). It would have been obvious to one of ordinary skills in the art before the effective filing of the claimed invention to modify Yoon so that the support structure is “electrically” connected to the external electrical connection (170) for the substrate. The ordinary artisan would have been motivated to modify Yoon for at least the purpose of using the external terminals to connect to the pads (190) to an external voltage source, thus using an electrical connection to the substrate to power the first chip, and powering the multichip package.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yoon in view of Chi (US 20120182650), hereinafter Chi.
Regarding claim 11, Yoon teaches the multichip package (refer to Figured 12A-B) of claim 10, but does not teach “wherein the external electrical connection provides access to a device external to the multichip package, wherein the device is a cooler, heat sink, or an electrostatic discharge (ESD) protection device”. However, Yoon teaches that the pads (190) of substrate (100) may be configured to transmit power voltage or a ground voltage to the first chip (200A), second chip (200B) and other chips (para 184). Further, Chi (US 20120182650) teaches a chip package (comprising 205, see Figure 2a and para 16) with at least a first solder ball (25, para 16) for external electrical connection (para 16), wherein the external electrical connection provides access to a device (2071, para 17) external to the chip package (comprising 205), wherein the device (2017) is an electrostatic discharge (ESD) protection device (para 17 describes “a plurality of ESD protection devices 2071”). It would have been obvious to one of ordinary skills in the art before the effective filing of the claimed invention to modify Yoon so that the external electrical connection provides access to a device external to the multichip package, wherein the device is an electrostatic discharge (ESD) protection device. The ordinary artisan would have been motivated to modify Yoon for at least the purpose of using a known configuration of ESD protection device (see para 19 of Chi) to prevent permanent damage when to the multichip package when subjected to high voltages (see para 5 of Chi).
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Conclusion
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/AJAY ARORA/Primary Examiner, Art Unit 2892
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