Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 7, 15, 16, 19, and 20 are rejected as unpatentable under 35 USC 103 over Donovan et al., U.S. 2020/0326425 (see IDS) in view of Pajkic et al., U.S. 2022/0029386 and Johnson, U.S. 2004/0033637.
On claim 1, Donovan cites except as underlined:
A system comprising:
a mounting structure;
[0025] FIG. 9 illustrates an embodiment of a LIDAR system array according to the present teaching in which the physical connection to the array enables a denser layout for the associated electronic circuits on the printed circuit board (PCB).
a driver affixed to the mounting structure;
figure 6 and [0022] high-side driver
an array of vertical-cavity service-emitting lasers (VCSELs) connected to an anode fanout and a cathode fanout, wherein the driver comprises a firing circuit configured to cause one or more of the VCSELs to emit light using the anode fanout and the cathode fanout;
figure 5k. For example, diodes V31 -V33 are coupled via anode and cathode fanouts.
one or more capacitors adhered to the mounting structure and connected to the cathode fanout or the anode fanout, wherein the one or more capacitors are configured to provide energy to the array of VCSELs;
[0020] FIG. 5K illustrates an electrical schematic diagram of the matrix-addressable laser drive circuit described in connection with FIG. 5J, but configured with the low-side capacitive discharge circuit in the capacitor discharge mode for laser diode 2,2 (second row and second column) according to one embodiment of the present teaching.
a growth layer, wherein the array of VCSELs, the one or more capacitors, the anode fanout, and the cathode fanout are disposed within the growth layer; and
an epoxy structure that encapsulates (i) the mounting structure and (ii) the array of VCSELs, the driver, or the one or more capacitors, or the growth layer.
Regarding the excepted claim limitations, Donovan, as previously stated and figure 5K, discloses at least substrates to include mounting components as illustrate on figure 5K. However, Donovan doesn’t disclose the substrate as being epoxy. ‘
In the same art of VCSEL circuit construction, Pajkic cites:
[0025] It is essential for the technical solution according to the invention that a light emitter unit with a VCSEL chip does not have a fixed substrate and a rigid housing, but that the VCSEL chip and, if required, further components of the light emitter unit are encapsulated or injection-molded at least in an edge region with a suitable material, for example epoxy resin provided with a filler. Various processes are known for achieving such a package-free encapsulation of the VCSEL chip, with other optical components of a light emitter unit with VCSEL chip also being encapsulated, if necessary, at least in the edge region. The processes in question include, for example, transfer molding, compression molding and film-assisted transfer molding. In general, it is also conceivable to encapsulate the VCSEL chip and, if required, the other electronic and/or optical elements of the light emitter unit with a suitable encapsulation material, such as silicone, epoxy resin or a composite, in each case with or without special fillers.
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to include into Donovan’s VCSEL circuitry the use of substrates employing epoxy construction such that the claimed invention is realized. One of ordinary skill would have included such a feature for environmental protection.
Regarding the excepted: a growth layer, wherein the array of VCSELs, the one or more capacitors, the anode fanout, and the cathode fanout are disposed within the growth layer, Donovan and Pajkic, above, disclosed embodiments involving VCSEL circuitry. However, neither reference discloses the use of a growth layer to arrange the cited VCSELs and the associated components.
In the same art of VCSEL manufacturing, Johnson cites:
[0039] As illustrated in the example of FIG. 3, islands of InGaAs 315 begin to form during growth, causing misfit dislocations. But when atomic hydrogen is used on the growth surface, the layers do not form significant steps, causing growth of flatter layers. Atomic hydrogen treatment during alloy layer growth, therefore, results in flatter, more uniform active layers within VCSELs than has been possible prior to processing VCSEL devices without hydrogen. As a result, long wavelength VCSEL performance is made more easily possible on GaAs.
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Donovan and Pajkic’s VCSELs to be manufactured using Johnson’s embodiment such that the claimed invention is realized. Like Donovan and Pajkic, Johnson discloses a known way to formulate VCSELs, but this time using purposeful growth (or epitaxy) to manufacture VCSEL circuits. As Johnson disclosed above, hydrogen is applied to the grown surface in order to influence the manufacture of the VCSEL circuitry. Thus, one of ordinary skill, apprised of Johnson’s embodiment, would have modified Donovan and Pajkic’s VCSEL circuits to produce an embodiment meeting the claimed invention.
On claim 2, Donovan cites:
The system of claim 1, wherein the VCSELs are bottom-emitting VCSELs.
[0007] FIG. 2 illustrates a perspective view of a structure of a known bottom-emitting Vertical Cavity Surface Emitting Laser (VCSEL) that can be used in a LIDAR system according to the present teaching.
On claim 3, Donovan cites except as underlined:
The system of claim 1, wherein the mounting structure comprises a polyimide printed circuit board (PCB), a rigid PCB, a ceramic PCB, or a glass PCB.
Donovan cites:
[0077] FIG. 9 illustrates an embodiment of a LIDAR system mounted VCSEL array chip 900 on a carrier 902 according to the present teaching. The physical connection to the array enables a denser layout for the associated electronic circuits on a printed circuit board (PCB) substrate.
Donovan doesn’t cite the PCB as being “rigid.
However, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to include into Donovan the feature of making the cited PCB rigid in construction. Rigid construction allows for the ease of construction and placement of PCBs into an enclosure.
On claim 4, Donovan cites:
The system of claim 1, wherein the driver comprises one or more anode switches connected to the anode fanout
Figure 5K, switches HS1-HS3 are connected to the anodes of V11 -V13
or one or more cathode switches connected to the cathode fanout.
On claim 7, Donovan cites:
The system of claim 1, wherein the driver comprises one or more anode switches
Figure 5K, switches HS1-HS3 are connected to the anodes of V11 -V13
or one or more cathode switches.
On claim 15, Donovan cites:
The system of claim 1, further comprising one or more heating elements configured to maintain the array of VCSELs at a predetermined or stable temperature.
[0082] For example, assuming the material properties of GaAs for specific heat and density, a pulse of 1 μJ into a junction 2 microns thick, and 100 microns in diameter, would result in a temperature rise of −9° C. for that junction. A 20V/10 A square pulse of 5 nsec in duration is equivalent to 1 μJ energy. The resulting transient temperature rise will be on the order of only a few degrees and thus will likely not be sufficient to degrade the reliability of the device.
The claimed “heating element” is the cited voltage applied to a GaAs device described above that causes the temperature to rise.
On claim 16, Donovan cites:
The system of claim 1, further comprising one or more cooling elements configured to maintain the array of VCSELs at a predetermined or stable temperature.
[0082] For example, assuming the material properties of GaAs for specific heat and density, a pulse of 1 μJ into a junction 2 microns thick, and 100 microns in diameter, would result in a temperature rise of −9° C. for that junction. A 20V/10 A square pulse of 5 nsec in duration is equivalent to 1 μJ energy. The resulting transient temperature rise will be on the order of only a few degrees and thus will likely not be sufficient to degrade the reliability of the device.
The claimed “cooling element” is the cited voltage applied to a GaAs device described above to keep the device from overheating.
On claim 19, Donovan cites except as underlined:
A method comprising:
affixing a driver to a mounting structure;
[0025] FIG. 9 illustrates an embodiment of a LIDAR system array according to the present teaching in which the physical connection to the array enables a denser layout for the associated electronic circuits on the printed circuit board (PCB).
connecting an array of vertical-cavity service-emitting lasers (VCSELs) to an anode fanout and a cathode fanout,
Figure 5G &5H, switches HS1-HS3 are connected to the anodes of V11 -V13, and , switches LS1-LS3 are connected to the anodes of V11 -V31
wherein the driver comprises a firing circuit configured to cause one or more of the VCSELs to emit light using the anode fanout and the cathode fanout;
see above
adhering one or more capacitors to the mounting structure;
connecting the one or more capacitors to the cathode fanout or the anode fanout, wherein the one or more capacitors are configured to provide energy to the array of VCSELs;
Figure 5G &5H, capacitors C1-C3 connected to the anodes of V11 -V31
encapsulating the array of VCSELs the one or more capacitors, the anode fanout, and the cathode fanout within a growth layer; and
and
encapsulating (i) the mounting structure and (ii) the array of VCSELs, the driver, or the one or more capacitors or the growth layer using an epoxy structure.
Regarding the excepted claim limitations, Donovan, as previously stated, includes a printed circuit board to mount the claimed components. However, Donovan doesn’t disclose the substrate as being “epoxy.”
In the same art of VCSEL circuit construction, Pajic cites:
[0025] It is essential for the technical solution according to the invention that a light emitter unit with a VCSEL chip does not have a fixed substrate and a rigid housing, but that the VCSEL chip and, if required, further components of the light emitter unit are encapsulated or injection-molded at least in an edge region with a suitable material, for example epoxy resin provided with a filler. Various processes are known for achieving such a package-free encapsulation of the VCSEL chip, with other optical components of a light emitter unit with VCSEL chip also being encapsulated, if necessary, at least in the edge region. The processes in question include, for example, transfer molding, compression molding and film-assisted transfer molding. In general, it is also conceivable to encapsulate the VCSEL chip and, if required, the other electronic and/or optical elements of the light emitter unit with a suitable encapsulation material, such as silicone, epoxy resin or a composite, in each case with or without special fillers.
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to include into Donovan’s VCSEL circuitry the use of substrates employing epoxy construction such that the claimed invention is realized. One of ordinary skill would have included such a feature for environmental protection.
Regarding the excepted: encapsulating the array of VCSELs the one or more capacitors, the anode fanout, and the cathode fanout within a growth layer;
Donovan and Pakjic, above, disclosed embodiments involving VCSEL circuitry. However, neither reference discloses the use of a growth layer to arrange the cited VCSELs and the associated components.
In the same art of VCSEL manufacturing, Johnson cites:
[0039] As illustrated in the example of FIG. 3, islands of InGaAs 315 begin to form during growth, causing misfit dislocations. But when atomic hydrogen is used on the growth surface, the layers do not form significant steps, causing growth of flatter layers. Atomic hydrogen treatment during alloy layer growth, therefore, results in flatter, more uniform active layers within VCSELs than has been possible prior to processing VCSEL devices without hydrogen. As a result, long wavelength VCSEL performance is made more easily possible on GaAs.
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Donovan and Pajkic’s VCSELs to be manufactured using Johnson’s embodiment such that the claimed invention is realized. Like Donovan and Pajkic, Johnson discloses a known way to formulate VCSELs, but this time using purposeful growth (or epitaxy) to manufacture VCSEL circuits. As Johnson disclosed above, hydrogen is applied to the grown surface in order to influence the manufacture of the VCSEL circuitry. Thus, one of ordinary skill, apprised of Johnson’s embodiment, would have modified Donovan and Pajkic’s VCSEL circuits to produce an embodiment meeting the claimed invention.
On claim 20, Donovan cites except as underlined:
A method comprising:
causing, by a firing circuit of a driver, one or more vertical-cavity service-emitting lasers (VCSELs) within an array of VCSELs to emit light using an anode fanout and a cathode fanout, wherein the array of VCSELs is connected to the anode fanout and the cathode fanout, and wherein the driver is affixed to a mounting structure;
Figure 5G &5H, switches HS1-HS3 are connected to the anodes of V11 -V13, and , switches LS1-LS3 are connected to the anodes of V11 -V31
and
providing, by one or more capacitors adhered to the mounting structure and connected to the cathode fanout or the anode fanout, energy to the array of VCSELs, wherein the array of VCSELs, the one or more capacitors, the anode fanout, and the cathode fanout are disposed whing a grown later, and wherein an epoxy structure encapsulates (i) the mounting structure and (ii) the array of VCSELs, the driver, the one or more capacitors, or the growth layer.
Donovan discloses:
[0025] FIG. 9 illustrates an embodiment of a LIDAR system array according to the present teaching in which the physical connection to the array enables a denser layout for the associated electronic circuits on the printed circuit board (PCB).
Donovan doesn’t disclose the excepted claim limitations. In the same art of VCSEL circuit construction, Pajic cites:
[0025] It is essential for the technical solution according to the invention that a light emitter unit with a VCSEL chip does not have a fixed substrate and a rigid housing, but that the VCSEL chip and, if required, further components of the light emitter unit are encapsulated or injection-molded at least in an edge region with a suitable material, for example epoxy resin provided with a filler. Various processes are known for achieving such a package-free encapsulation of the VCSEL chip, with other optical components of a light emitter unit with VCSEL chip also being encapsulated, if necessary, at least in the edge region. The processes in question include, for example, transfer molding, compression molding and film-assisted transfer molding. In general, it is also conceivable to encapsulate the VCSEL chip and, if required, the other electronic and/or optical elements of the light emitter unit with a suitable encapsulation material, such as silicone, epoxy resin or a composite, in each case with or without special fillers.
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to include into Donovan’s VCSEL circuitry the use of substrates employing epoxy construction such that the claimed invention is realized. One of ordinary skill would have included such a feature for environmental protection.
Regarding the excepted: wherein the array of VCSELs, the one or more capacitors, the anode fanout, and the cathode fanout are disposed within a growth layer, Donovan and Pajkic, above, disclosed embodiments involving VCSEL circuitry. However, neither reference discloses the use of a growth layer to arrange the cited VCSELs and the associated components.
In the same art of VCSEL manufacturing, Johnson cites:
[0039] As illustrated in the example of FIG. 3, islands of InGaAs 315 begin to form during growth, causing misfit dislocations. But when atomic hydrogen is used on the growth surface, the layers do not form significant steps, causing growth of flatter layers. Atomic hydrogen treatment during alloy layer growth, therefore, results in flatter, more uniform active layers within VCSELs than has been possible prior to processing VCSEL devices without hydrogen. As a result, long wavelength VCSEL performance is made more easily possible on GaAs.
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Donovan and Pajkic’s VCSELs to be manufactured using Johnson’s embodiment such that the claimed invention is realized. Like Donovan and Pajkic, Johnson discloses a known way to formulate VCSELs, but this time using purposeful growth (or epitaxy) to manufacture VCSEL circuits. As Johnson disclosed above, hydrogen is applied to the grown surface in order to influence the manufacture of the VCSEL circuitry. Thus, one of ordinary skill, apprised of Johnson’s embodiment, would have modified Donovan and Pajkic’s VCSEL circuits to produce an embodiment meeting the claimed invention.
Regarding the excepted “epoxy structure,” Donovan, as previously stated and figure 5K, discloses at least substrates to include mounting components as illustrate on figure 5K. However, Donovan doesn’t disclose the substrate as being epoxy encapsulated. ‘
In the same art of VCSEL circuit construction, Pajkic cites:
[0025] It is essential for the technical solution according to the invention that a light emitter unit with a VCSEL chip does not have a fixed substrate and a rigid housing, but that the VCSEL chip and, if required, further components of the light emitter unit are encapsulated or injection-molded at least in an edge region with a suitable material, for example epoxy resin provided with a filler. Various processes are known for achieving such a package-free encapsulation of the VCSEL chip, with other optical components of a light emitter unit with VCSEL chip also being encapsulated, if necessary, at least in the edge region. The processes in question include, for example, transfer molding, compression molding and film-assisted transfer molding. In general, it is also conceivable to encapsulate the VCSEL chip and, if required, the other electronic and/or optical elements of the light emitter unit with a suitable encapsulation material, such as silicone, epoxy resin or a composite, in each case with or without special fillers.
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to include into Donovan’s VCSEL circuitry the use of substrates employing epoxy construction such that the claimed invention is realized. One of ordinary skill would have included such a feature for environmental protection.
Claim 5 is rejected as unpatentable under 35 USC 103 over Donovan et al., U.S. 2020/0326425 in view of Pajkic et al., U.S. 2022/0029386 and Johnson, U.S. 2004/0033637 and Wang et al., U.S. 2018/0102442..
On claim 5, Donovan cites except as underlined:
The system of claim 1, wherein the driver comprises a silicon driver that includes an application-specific integrated circuit (ASIC).
[0050] In one embodiment, the solid state LIDAR system of the present teaching uses VCSEL devices that are assembled using heterogeneous integration techniques. For example, these devices can be flip-chip bonded to silicon electronics to provide a highly compact method of connecting to and electrically driving the VCSEL.
As discussed above, Donovan cites using silicon electronics to drive VCSELs. Donovan doesn’t disclose these electronics as “ASICS.”
In the same art of VCSELs, Wang cites:
[0203] FIG. 8 is a diagram illustrating a monolithically integrated single silicon chip that can include single and/or multiple combinations of devices, according to some embodiments. Silicon chip 800 can any combination of the following devices: MSPDs; MSAPDs; vertical cavity surface emitting lasers (VCSEL) that are either wafer bonded to the chip and/or have a precision cavity for dropping the VCSEL into as in a silicon platform; CMOS/BiCMOS ASICs configured for functions such as signal processing, amplifying, transmission, storage, conditioning, analyzing, and/or configured as laser drivers.
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to include into Donovan the silicon ASIC component features of Wang such that the claimed invention is realized. Wang discloses a known embodiment for using silicon ASIC drivers. One of ordinary skill would have included this type of device as another known alternative embodiment for driving VCSELs.
Claim 6 is rejected as unpatentable under 35 USC 103 over Donovan et al., U.S. 2020/0326425 in view of Pajkic et al., U.S. 2022/0029386 and Johnson, U.S. 2004/0033637 and Murugan et al., U.S. 2009/0166889.
On claim 6, Donovan cites except as underlined:
The system of claim 1, wherein the driver is affixed to the mounting structure using a bonding agent, and wherein the bonding agent comprises an epoxy die-bond.
Donovan and Pajkic, as in the rejection of claim 1, discloses a feature of using epoxy structure, for the mounting structure. Donovan doesn’t disclose the use of an epoxy die-bond as a bonding agent for the mounting structure.
In the related art of integrated circuit packaging, Murugan cites:
[0032] As illustrated in the example of FIG. 5E, the integrated circuit 118 is then attached to the protective layer 114 via the epoxy layer 116 (e.g., an epoxy die bond) (block 430).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to include into Donovan the epoxy die-bond feature of Murugan such that the claimed invention is realized. Murugan discloses a known feature of using epoxy die-bond circuit construction and one of ordinary skill would have incorporated this known manufacturing technique as an available known way to construct the claimed circuit.
Claims 8-9 are rejected as unpatentable under 35 USC 103 over Donovan et al., U.S. 2020/0326425 in view of Pajkic et al., U.S. 2022/0029386 and Johnson, U.S. 2004/0033637 and Yamada et al., U.S. 2005/0087747.
On claim 8, Donovan cites except as underlined:
The system of claim 1, wherein the one or more capacitors are connected to the cathode fanout using a metallic trace.
Donovan cites:
[0025] FIG. 9 illustrates an embodiment of a LIDAR system array according to the present teaching in which the physical connection to the array enables a denser layout for the associated electronic circuits on the printed circuit board (PCB).
Donovan doesn’t disclose the connections in the PCB as using a metallic trace.
In the related art of circuit board construction, Yamada cites:
[0069] The circuit wiring board 10 has a copper wiring pattern, an insulating layer and a build-up copper wiring layer formed in this order on the copper-plated through-holes. The circuit wiring board 10 having the aforementioned structure is produced in the following manner, for example.
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to include into Donovan the circuit manufacturing feature of Yamada wherein the connected anodes to the cited capacitors are joined via plated wiring such that the claimed invention is realized. One of ordinary skill would have incorporated Yamada’s wiring as a known connection technique and one of ordinary skill would have incorporated this known manufacturing process as an available known way to construct the claimed circuit.
On claim 9, Donovan, Pajkic, and Yamada cites:
The system of claim 8, wherein the metallic trace comprises a plated metal.
See the rejection of claim 8 wherein Yamada cites:
[0069] The circuit wiring board 10 has a copper wiring pattern, an insulating layer and a build-up copper wiring layer formed in this order on the copper-plated through-holes. The circuit wiring board 10 having the aforementioned structure is produced in the following manner, for example.
Claim 10 is rejected as unpatentable under 35 USC 103 over Donovan et al., U.S. 2020/0326425 in view of Pajkic et al., U.S. 2022/0029386 and Johnson, U.S. 2004/0033637 and Glezer et al., U.S. 2005/0142033.
On claim 10, Donovan and Yamada cites except:
The system of claim 8, wherein the metallic trace comprises a surface trace through the encapsulating epoxy structure or a laser-cut via through the encapsulating epoxy structure.
As previously disclosed, Yamada cites:
[0069] The circuit wiring board 10 has a copper wiring pattern, an insulating layer and a build-up copper wiring layer formed in this order on the copper-plated through-holes. The circuit wiring board 10 having the aforementioned structure is produced in the following manner, for example.
Yamada doesn’t specifically cite the through-hole as a laser-cut via.
In the related art of circuit board construction, Glezer cites:
[0912] The conductive pads were connected to screen-printed electrical contacts on the back of the plate (also carbon ink over silver ink) through laser-cut through-holes in the Mylar substrate that filled with conductive material during the screen-printing steps.
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to include into Yamada the use of laser—cut through holes such that the claimed invention is realized. Glezer discloses a known way to provide vias in a circuit board using laser cutting and one of ordinary skill would have included this feature as another known way in the art for providing connections in a circuit.
Claim 11 is rejected as unpatentable under 35 USC 103 over Donovan et al., U.S. 2020/0326425 in view of Pajkic et al., U.S. 2022/0029386 and Johnson, U.S. 2004/0033637 and Cok et al., U.S. 2018/0174932.
On claim 11, Donovan and Pakjic cites except as underlined:
The system of claim 1, wherein the one or more capacitors comprise a surface-mounted device (SMD).
Donovan previously disclosed using printed circuit boards in [0045] as well as capacitors in figure 5K. Donovan doesn’t disclose using SMDs.
In the similar art of printed circuit repair, Cok cites:
[0011] Surface-mount technology (SMT) is widely used in the electronics industry to provide high-density printed-circuit boards (PCBs). In particular, a well-developed and inexpensive infrastructure exists for making and integrating two-terminal surface-mount devices, such as resistors or capacitors, into printed circuit boards.
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to include into Donovan’s PCB the use of SMD capacitors, as disclosed in Cok. The use of surface mounted capacitors is well known and “widely used in the electronics industry” and one of ordinary skill, apprised by this well known use, would have included this type of component as a known component commonly use in the industry.
Claims 12, 13, and 14 are rejected as unpatentable under 35 USC 103 over Donovan et al., U.S. 2020/0326425 in view of Pajkic et al., U.S. 2022/0029386 and Johnson, U.S. 2004/0033637 and Oka et al., U.S. 2022/0037853.
On claim 12, Donovan cites except:
The system of claim 1, wherein the one or more capacitors comprise a bank of capacitors. As shown, Donovan disclosed:
Figure 5G &5H, capacitors C1-C3 connected to the anodes of V11 -V31
Donovan doesn’t disclose any one of the capacitors as being provided as “a bank.”
In the similar art of light source drive circuits, Oka cites:
Figure 2 and [0036] The capacitor 121 is an example of a “charge storage device.” A first end of the capacitor 121 is connected to the output of the voltage-current controller 111, and a second end thereof is grounded. The capacitor 121 is charged with electric power (DC voltage V0) supplied from the voltage-current controller 111. Examples of the capacitor 121 include a low equivalent series inductance (ESL) monolithic ceramic capacitor and electrolytic capacitor. Note that the capacitor 121 may be constructed of a plurality of capacitors connected in parallel.
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to include into Donovan the feature of constructing a capacitor as a plurality of capacitors as noted in Oka. Parallelling capacitors is known in the art for increasing the overall capacitance of a required capacitor in a circuit and one of ordinary skill would have included such a feature to increase the stored electrical energy in a plurality of capacitors, which would be considered a “bank of capacitors,” as opposed to a single capacitor of lesser value.
On claim 13, Donovan cites: The system of claim 12, wherein each capacitor is configured to provide energy to a separate VCSEL in the array of VCSELs.
See Figure 5H. The cited discharge path for C2 for VCSEL V22. This happens when switches HS2 and LS2 are closed. This discharge path to energize the VCSEL is a model for the rest of the VCSELs when their respective HSx and LSx switches are closed.
On claim 14, Donovan cites:
The system of claim 12, wherein each capacitor is configured to provide energy to all VCSELs in the array of VCSELs.
Figure 5H, capacitors C1-C3.
Claim 17 is rejected as unpatentable under 35 USC 103 over Donovan et al., U.S. 2020/0326425 in view of Pajkic et al., U.S. 2022/0029386 and Johnson, U.S. 2004/0033637 and Donze et al., U.S. 2005/0201188.
On claim 17, Donovan cites except as underlined:
The system of claim 1, further comprising:
one or more heating elements or one or more cooling elements configured to maintain the array of VCSELs at a predetermined or stable temperature;
[0082] For example, assuming the material properties of GaAs for specific heat and density, a pulse of 1 μJ into a junction 2 microns thick, and 100 microns in diameter, would result in a temperature rise of −9° C. for that junction. A 20V/10 A square pulse of 5 nsec in duration is equivalent to 1 μJ energy. The resulting transient temperature rise will be on the order of only a few degrees and thus will likely not be sufficient to degrade the reliability of the device.
and
a controller configured to control the one or more heating elements or the one or more cooling elements based on an ambient temperature in a surrounding environment.
[0024] FIG. 8 illustrates the voltages induced at nodes in a matrix while energizing a single laser within a two-dimensional array with row/column matrix addressability according to an embodiment of a matrix-address laser drive circuit controller of the present teaching.
However, Donovan doesn’t disclose the excepted claim limitations.
In the similar art of temperature control, Donze cites:
[0045] Voltage controller 22, knowing then the rate of increase of temperature, and the thermal time constant of the chip and package (from product data 24), can compute a final chip temperature (assuming chip power and ambient temperature were to stay constant). If the computed final chip temperature were to exceed the limit temperature, voltage controller 22 effects a reduction in VDD 27 voltage even before a thermal fault is detected.
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to include into Donovan the voltage control ambient temperature determination feature of Donze wherein voltage control to control temperature is based on the known ambient temperature. One of ordinary skill would have included this known feature to control voltages disclosed in Donovan, [0082] to provide a suitable temperature where the GaAs devices would maintain a stable temperature.
Claim 18 is rejected as unpatentable under 35 USC 103 over Donovan et al., U.S. 2020/0326425 in view of Pajkic et al., U.S. 2022/0029386 and Johnson, U.S. 2004/0033637 and Donze et al., U.S. 2005/0201188 and Zhao et al., U.S. 2021/0403023.
On claim 18, Donovan and Donze cites except as underlined:
The system of claim 17, wherein the controller comprises a temperature sensor configured to measure the ambient temperature in the surrounding environment.
As was disclosed in the rejection of claim 17, Donze discussed an embodiment wherein a voltage controller, apprised of known ambient temperature, regulates voltages to a chip that translates to chip temperatures not exceeding the chip’s specified thermal limits. However, neither reference discloses using a temperature sensor to determine ambient temperature. In the related art of environment sensing, Zhao cites:
[0048] The sensors also may include environmental sensors 268 such as a precipitation sensor and/or ambient temperature sensor.
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to include into Donovan and Donze the temperature sensor of Zhao such that voltage regulation to an integrated circuit’s power supply takes into account ambient temperatures measured via a temperature sensor. Since temperature is likely subject to change, one of ordinary skill would have include measured ambient temperature data to the voltage control for an up to day voltage adjustment.
Response to Arguments
Applicant’s arguments with respect to the rejections of claims 1, 19, and 20 regarding the claimed “growth layer” have been carefully reviewed. However, the claimed “growth layer” was not previously discussed in a prior examination, making the applicant’s arguments moot since the amendment required a new search and consideration.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time.
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CAL EUSTAQUIO whose telephone number is (571)270-7229. The examiner can normally be reached on 8am-5pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Brian Zimmerman, can be reached at (571) 272-3059. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application lnformation Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAlR only. For more information about the PAlR system, see http:/lpair-direct.uspto.gov. Should you have questions on access to the Private PAlR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-91 99 (IN USA OR CANADA) or 571-272-1000.
/CAL J EUSTAQUIO/Examiner, Art Unit 2686
/BRIAN A ZIMMERMAN/Supervisory Patent Examiner, Art Unit 2686
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