DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
2. The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
The following claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, as a means-plus-function limitation because the limitation uses the phrase “means for” and recites a function without reciting sufficient structure for performing that function:
3. Such claim limitation is:
A changing means capable of changing a timing.
The corresponding structure in the disclosure for a “changing means” is taken to include a computer system (as taught in [0020]).
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier.
4. Such claim limitation(s) is/are:
A processing mechanism
A sample exchange mechanism
A control mechanism
Mechanisms of the load lock chamber
A mechanism accompanied by an operation that generates vibration
An adjustment mechanism
A mechanism that observes and/or processes a semiconductor by using a charged particle beam
A mechanism that performs exposure by using light
A first control device
A second control device
A third control device
A fourth control device
The entire device
A conveyance device
The corresponding structure in the disclosure for a “processing mechanism” is taken to include a column that is equipped with an electron gun that irradiates the wafer with a charged particle beam (as taught in [0018]).
The corresponding structure in the disclosure for a “sample exchange mechanism” is taken to include a robot that conveys a wafer (as taught in [0018]).
The corresponding structure in the disclosure for a “control mechanism” is taken to include a computer system (as taught in [0017])
The corresponding structure in the disclosure for “mechanisms” of the load lock chamber is taken to include gate valves (as taught in [0019])
The corresponding structure in the disclosure for a “mechanism” accompanied by an operation that generates vibration is taken to include a gate valve (as taught in [0007]).
The corresponding structure in the disclosure for an “adjustment mechanism” for adjustment air pressure in the load lock chamber is taken to include a vacuum pump (as taught in [0019]).
The corresponding structure in the disclosure for a “mechanism” that observes and/or processes a semiconductor by using a charged particle beam is taken to include a column that is equipped with an electron gun that irradiates the wafer with a charged particle beam (as taught in [0018]).
The corresponding structure in the disclosure for a “mechanism” that performs exposure by using light is taken to include a light source.
The corresponding structure in the disclosure for a “first control device” that controls the operation of the mechanism accompanied by an operation that generates vibration is taken to include a valve device control unit in a computer system (as taught in [0020]).
The corresponding structure in the disclosure for a “second control device” that controls a conveyance device conveying the semiconductor wafer is taken to include a conveyance device control unit in a computer system (as taught in [0020]).
The corresponding structure in the disclosure for a “third control device” that controls the processing mechanism processing the semiconductor wafer is taken to include an electron optical system control unit in a computer system (as taught in [0020]).
The corresponding structure in the disclosure for a “fourth control device” that controls the controls the operation of the entire device is taken to include a control unit in a computer system (as taught in [0020]).
The corresponding structure in the disclosure for a “conveyance device” conveying the semiconductor wafer is taken to include robots related to wafer conveyance (as taught in [0020]).
Claim Rejections - 35 USC § 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
6. Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
7. Regarding claim 1:
Claim 1 recites “an operation of a mechanism accompanied by an operation that generates vibration”. Two “an operation” references make it unclear if they refer to the same operation or two distinct operations. Claims 2-10 depends on claim 1 and are also rejected as indefinite.
8. Regarding claim 2:
Claim 2 recites the limitation “the load lock chamber”. Claim 1 on which claim 2 depends recites a plurality of load lock chambers. There is insufficient antecedent basis for this limitation in the claim. It is unclear which load lock chamber the applicant refers to. Claim 4 depends on claim 2 and is also rejected as indefinite.
9. Regarding claim 3:
Claim limitation a “mechanism” that performs exposure by using light invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The written description does not describe what structure performs light-based exposure, leaving a POSITA unable to determine the scope of that alternative with reasonable certainty. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
10. Regarding claim 5:
Claim 5 recites the limitation “the load lock chamber”. Claim 1 on which claim 5 depends recites a plurality of load lock chambers. There is insufficient antecedent basis for this limitation in the claim. It is unclear which load lock chamber the claim refers to.
11. Regarding claim 6:
Claim 6 recites the limitation “the load lock chamber”. Claim 1 on which claim 6 depends recites a plurality of load lock chambers. There is insufficient antecedent basis for this limitation in the claim. It is unclear which load lock chamber the claim refers to. In addition, claim 6 recites “an operation of the mechanism accompanied by an operation”. “An operation” is already recited in claim 1. It is unclear if the operation in claim 6 refers to the same operation in claim 1 or not. Claim 7 depends on claim 6 and is also rejected as indefinite.
12. Regarding claim 7:
The applicant recites “a time required for the process is calculated from a sum”. It is unclear if the applicant means the sum of the irradiation time, movement time, and the number of points. It appears that the applicant means the number of points multiplied by a sum of the irradiation time and movement time (as suggested in [0069] of the instant specification).
13. Regarding claim 8:
Claim 8 recites the limitation “the entire device”. Claim 1 on which claim 8 depends does not recite any entire device. There is insufficient antecedent basis for this limitation in the claim. Claim 9 depends on claim 8 and is also rejected as indefinite.
14. Regarding claim 9:
Claim 8 recites “an operation of a mechanism” and “an operation generating vibration”. “an operation” and “a mechanism” is already recited in claim 1. It is unclear if the operation and mechanism in claim 9 refers to the same operation and mechanism in claim 1 or not.
15. Regarding claim 10:
Claim 10 recites the limitation "the conveyance device". Claim 1 on which claim 10 depends does not recite any conveyance device. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
16. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
17. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
18. Claims 1, 3, 8-10 are rejected under 35 U.S.C 103 as being unpatentable over Hirayanagi (JP 2004158616A) in view of Kroeker (US 6250869).
19. Regarding claim 1:
Hirayanagi teaches a semiconductor processing apparatus comprising ([0001] teaches an exposure apparatus for processing semiconductor integrated circuit and the like):
a sample chamber ([0038] teaches an exposure chamber) that includes a processing mechanism for processing a semiconductor wafer therein (The “processing mechanism” is interpreted under 35 U.S.C. 112(f) to include a column that is equipped with an electron gun that irradiates the wafer with a charged particle beam. [0003] teaches the electron beam exposure apparatus. [0015] teaches the electron gun 1. [0038] teaches an electron beam column);
a load lock chamber that carries the semiconductor wafer into the sample chamber ([0003] teaches a load lock chamber 111. [0004]-[0005] teaches that the wafer is transferred from the load lock chamber 111 to the load chamber 103 and then to the exposure chamber 101); and a sample exchange mechanism that exchanges semiconductor wafers between the sample chamber and the load lock chamber (The “sample exchange mechanism” is interpreted under 35 U.S.C. 112(f) to include a robot that conveys a wafer. [0005] teaches that the wafer is transferred to exposure chamber 101 by the vacuum transfer robot 107),
wherein the semiconductor processing apparatus includes a control mechanism that controls operations of mechanisms of the load lock chamber (the “control mechanism” is interpreted under 35 U.S.C. 112(f) to include a computer system. The “mechanisms” is interpreted under 35 U.S.C. 112(f) to include gate valves. [0013] teaches the controller controls to stop the operation of the transfer device during a predetermined processing step during the exposure sequence. [0004]-[0006] teaches that vibration is generated by opening and closing operations of the gate valves 109 and 113. The controller is equivalent to the computer system because the controller performs the same function in substantially the same way and produces substantially the same result) so that an operation of a mechanism accompanied by an operation that generates vibration is performed in a load lock chamber (The “mechanism” accompanied by an operation that generates vibration is interpreted under 35 U.S.C. 112(f) to include a gate valve. [0004]-[0006] teaches that vibration is generated by opening and closing operations of the gate valves 109 and 113. The vibration affects the load lock chamber).
Hirayanagi fails to teach a plurality of load lock chambers that carry the semiconductor wafer into the sample chamber; and exchanging semiconductor wafers between the sample chamber and each of the plurality of load lock chambers, controlling operations of mechanisms of the plurality of load lock chambers so that an operation of a mechanism accompanied by an operation that generates vibration is performed in a load lock chamber in which the semiconductor wafer is not exchanged among the plurality of load lock chambers at a timing when one of the plurality of load lock chambers is exchanging the semiconductor wafer with the sample chamber.
Kroeker teaches a plurality of load lock chambers that carry the semiconductor wafer into the sample chamber (column 2 lines 15-31 teaches two or more load lock chambers mounted on a central chamber which can be mounted on a single opening in a vacuum chamber such as a substrate processing platform for making integrated circuits on silicon wafers); and exchanging semiconductor wafers between the sample chamber and each of the plurality of load lock chambers (columns 2 lines 15-31 and column 3 lines 35-50 teach that each load lock region has its own transfer mechanism exchanging wafers with the central chamber),
controlling operations of mechanisms of the plurality of load lock chambers so that an operation of a mechanism accompanied by an operation that generates vibration is performed in a load lock chamber (The “mechanism” accompanied by an operation that generates vibration is interpreted under 35 U.S.C. 112(f) to include a gate valve. Column 8 lines 65-67 teaches a load lock valve between each load lock housing and the central housing. Column 3 lines 35-50 teaches that the second load lock region is loaded and pumped down to the desire pressure, which inherently generates vibration)
in which the semiconductor wafer is not exchanged among the plurality of load lock chambers (Column 3 lines 35-45 teaches that while the wafers are being processed, the second load lock region is loaded and pumped down to the desire pressure. When the second load lock region is pumped down, it is not the one exchanging wafers with the central housing. The first load lock region has already completed its exchange and its wafers are being processed. The second load lock region is the non-exchanging chamber at this point)
at a timing when one of the plurality of load lock chambers is exchanging the semiconductor wafer with the sample chamber (Column 3 lines 35-50 teaches that while the wafers are being processed, the second load lock region is loaded and pumped down to the desire pressure. Exchanging the semiconductor wafer with the sample chamber is interpreted under broadest reasonable interpretation to encompass the entire transfer operation of picking up from one chamber, transporting, placing in the other, which is a time-consuming sequence that overlaps with what Kroeker describes as part of “being processed” in column 3 lines 35-50).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to have modified Hirayanagi to include the plurality of load lock chambers and the sequency and timing of operating the load lock chamber in Kroeker. One of ordinary skill in the art would be motivated to make such modification to allow for continuous operation (Kroeker column 1 lines 32-43) so that no load chamber sits idle while the other chamber is occupied (Kroeker column 3 lines 35-50).
Regarding claim 3:
The above modified invention teaches the semiconductor processing apparatus according to claim 1. Hirayanagi further teaches that wherein the processing mechanism is at least one of a mechanism that observes and/or processes a semiconductor by using a charged particle beam (the “mechanism” is interpreted under 35 U.S.C 112(f) to include a column that is equipped with an electron gun. [0003] teaches the electron beam exposure apparatus. [0015] teaches the electron gun 1. [0038] teaches an electron beam column), and a mechanism that performs exposure by using light (the “mechanism” is interpreted under 35 U.S.C 112(f) to include light source. [0008] teaches that there’s no limitation on the type of energy beam used for exposure, light or the like can be used. A light source is inherently needed to produce such light).
Regarding claim 8:
The above modified invention teaches the semiconductor processing apparatus according to claim 1. Hirayanagi further teaches a first control device (The “first control device” is interpreted under 35 U.S.C. 112(f) to include a valve device control unit in a computer system) that controls the operation of the mechanism accompanied by an operation that generates vibration (the “mechanism” accompanied by an operation that generates vibration is interpreted under 35 U.S.C. 112(f) to include a gate valve. [0004]-[0006] teaches that vibration is generated by opening and closing operations of the gate valves 109 and 113. [0013] teaches the controller controls to stop the operation of the transfer device during a predetermined processing step during the exposure sequence. Pg. 1 teaches that the transfer device includes gate valves, which means that the controller controls the gate valves);
a second control device that controls a conveyance device conveying the semiconductor wafer (the “second control device” is interpreted under 35 U.S.C. 112(f) to include a conveyance device control unit in a computer system. The “conveyance device” is interpreted under 35 U.S.C. 112(f) to include robots related to wafer conveyance. [0013] teaches the controller controls to stop the operation of the transfer device during a predetermined processing step during the exposure sequence. Pg. 1 teaches that the transfer device includes robots, which means that the controller controls the robots);
a third control device that controls the processing mechanism processing the semiconductor wafer (the “third control device” is interpreted under 35 U.S.C. 112(f) to include an electron optical system control unit in a computer system. The “processing mechanism” is interpreted under 35 U.S.C. 112(f) to include a column that is equipped with an electron gun that irradiates the wafer with a charged particle beam. [0003] teaches the electron beam exposure apparatus. [0015] teaches the electron gun 1. [0038] teaches an electron beam column. [0013] teaches a controller that controls an exposure sequence, which means that the controller controls the exposure apparatus); and
a fourth control device that controls the operation of the entire device by transmitting control signals to the first to third control devices (the “fourth control device” is interpreted under 35 U.S.C. 112(f) to include a control unit in a computer system. [0043] teaches that the exposure sequence and the transport sequence are synchronized with reference to the reference time signal of the master clock of the controller).
Regarding claim 9:
The above modified invention teaches the semiconductor processing apparatus according to claim 8. Hirayanagi further teaches that wherein a signal for prohibiting an operation of a mechanism designated in advance among the mechanisms accompanied by an operation generating vibration (The “mechanism” accompanied by an operation that generates vibration is interpreted under 35 U.S.C. 112(f) to include a gate valve. [0004]-[0006] teaches that vibration is generated by opening and closing operations of the gate valves 109 and 113. The vibration affects the load lock chamber) is transmitted from the fourth control device to the first control device while performing the processing in the processing mechanism that processes the semiconductor wafer (pg. 1 teaches that the controller controls the operation of the transfer device to stop during a predetermined processing step during the exposure sequence),
the second and third control devices transmit completion of the processing in the processing mechanism that processes the semiconductor wafer to the fourth control device when the processing in the processing mechanism that processes the semiconductor wafer is completed ([0043] teaches that the exposure sequence and the transport sequence are synchronized with reference to the reference time signal of the master clock of the controller. Synchronization via master clock means the controller knows when each processing step completes. The exposure sequence signals its completion state through the master clock reference, which the transport sequence and exposure control both feeds back to the master controller), and
the fourth control device transmits, to the first control device, a signal for permitting the operation of the mechanism whose operation is prohibited and which is accompanied by an operation generating vibration (pg. 1 abstract teaches that a wafer exchange time, a stage movement time during exposure of each chip is used as the transfer system operation permission time, and the transfer system such as opening and closing of the gate valve and operation of the robot is operated. When the processing step completes, controller enters the permission window, which is the permission signal from the fourth control device to the first).
Regarding claim 10:
The above modified invention teaches the semiconductor processing apparatus according to claim 1. Hirayanagi further teaches that wherein the conveyance device conveying the semiconductor wafer includes a conveyance robot ([0004]-[0006] teaches driving of the transfer robots 107 and 115).
29. Claims 2, 4 are rejected under 35 U.S.C 103 as being unpatentable over Hirayanagi in view of Kroeker, further in view of Hatakeyama (US 20160307726).
Regarding claim 2:
Hirayanagi in view of Kroeker teaches the semiconductor processing apparatus according to claim 1. Hirayanagi further teaches that wherein the mechanism accompanied by an operation that generates vibration includes at least one of a gate valve for taking the semiconductor wafer into and out of the load lock chamber ([0003] teaches a gate valve 113 is provided at the entrance of the load lock chamber 111. The load lock chamber 111 is connected to the load chamber 103 via a gate valve 109. Both gates control wafer passage into and out of the lock chamber. [0006] teaches that vibration is generated by opening and closing operations of the gate valves 109 and 113), and
Hirayanagi in view of Kroeker does not specifically note an opening/closing valve of a pipe connected to an adjustment mechanism for adjusting air pressure in the load lock chamber.
However, Hatakeyama teaches an opening/closing valve of a pipe connected to an adjustment mechanism for adjusting air pressure in the load lock chamber (The “adjustment mechanism” for adjustment air pressure in the load lock chamber is interpreted under 35 U.S.C 112(f) to include a vacuum pump. [0352] teaches a vacuum pipe, a vacuum valve, and a vacuum pump that are used to exhaust and control vacuum level of a load-lock chamber).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to have modified Hirayanagi in view of Kroeker to include the vacuum pipe, vacuum valve, and vacuum pump in Hatakeyama. One of ordinary skill in the art would be motivated to make such modification to exhaust and control vacuum level in the load lock chamber (Hatakeyama [0352]).
Regarding claim 4:
The above modified invention teaches the semiconductor processing apparatus according to claim 2. Hirayanagi in view of Kroeker does not specifically note that wherein the pipe connected to the adjustment mechanism includes at least one of a pipe for allowing a predetermined gas to flow into the load lock chamber, a pipe connected to a roughing vacuum pump, and a pipe connected to a turbo molecular pump.
However, Hatakeyama teaches that wherein the pipe connected to the adjustment mechanism includes at least one of a pipe for allowing a predetermined gas to flow into the load lock chamber, a pipe connected to a roughing vacuum pump, and a pipe connected to a turbo molecular pump (the “adjustment mechanism” for adjustment air pressure in the load lock chamber is interpreted under 35 U.S.C 112(f) to include a vacuum pump. [0352] teaches a vacuum pipe, a vacuum valve, and a turbo molecular pump that are used to exhaust and control vacuum level of a load-lock chamber).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to have modified Hirayanagi in view of Kroeker to include the vacuum pipe, vacuum valve, and turbo molecular pump in Hatakeyama. One of ordinary skill in the art would be motivated to make such modification to exhaust and control vacuum level in the load lock chamber (Hatakeyama [0352]).
29. Claims 5-7 is rejected under 35 U.S.C 103 as being unpatentable over Hirayanagi in view of Kroeker, further in view of Takabatake (US 20210241993).
Regarding claim 5:
The above modified invention teaches the semiconductor processing apparatus according to claim 1. Hirayanagi in view of Kroeker does not specifically note that wherein the sample exchange mechanism conveys a sample in the sample chamber to the load lock chamber at a timing when the semiconductor wafer is carried from the load lock chamber to the sample chamber.
Takabatake teaches bidirectional exchange between the load lock chamber and the sample chamber in parallel ([0004] teaches that the door connecting the LC and the SC is opened, and the succeeding wafer and the preceding wafer are exchanged. [0015] teaches exchanging wafers in parallel).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to have modified Hirayanagi in view of Kroeker to include the parallel bidirectional exchange of different wafers as taught in Takabatake. One of ordinary skill in the art would be motivated to make such modification to allow for a time lag as small as possible when transporting a succeeding wafer in parallel with returning a preceding wafer (Takabatake [0015]).
Regarding claim 6:
The above modified invention teaches the semiconductor processing apparatus according to claim 1. Hirayanagi further teaches a changing means capable of changing a timing (The “changing means” is interpreted under 35 U.S.C. 112(f) to include a computer system. [0013]-[0014] teaches the controller that controls the exposure sequence and the transport sequence. The controller is equivalent to the computer system because the controller performs the same function in substantially the same way and produces substantially the same result)
when an operation of the mechanism accompanied by an operation that generates vibration is performed (The “mechanism” accompanied by an operation that generates vibration is interpreted under 35 U.S.C. 112(f) to include a gate valve. [0004]-[0006] teaches that vibration is generated by opening and closing operations of the gate valves 109 and 113. The vibration affects the load lock chamber).
Hirayanagi in view of Kroeker does not teach at least one of a time required for processing of the semiconductor wafer and a time required for evacuation of the load lock chamber.
However, Takabatake teaches at least one of a time required for processing of the semiconductor wafer (at least one of means any time required would suffice, and the other one is optional) and a time required for evacuation of the load lock chamber ([0059] teaches time required for evacuating a wafer changes depending on a process step and a material of the wafer. LC vacuum evacuation time is managed for each recipe)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to have modified Hirayanagi in view of Kroeker to include the evacuation time as a parameter to change the timing as taught in Takabatake. One of ordinary skill in the art would be motivated to make such modification to allow for a time lag as small as possible when transporting a succeeding wafer in parallel (Takabatake [0015]).
Regarding claim 7:
The above modified invention teaches the semiconductor processing apparatus according to claim 6, wherein the processing of the semiconductor wafer is processing for irradiating the semiconductor wafer with a charged particle beam (Hirayanagi [0003] teaches the electron beam exposure apparatus irradiating the wafer), and
a time required for the processing is calculated from a sum of a time required to irradiate one point on the semiconductor wafer with a charged particle beam and a time required to move the semiconductor wafer to irradiate the one point with the charged particle beam, and the number of points of the semiconductor wafer which are irradiated with the charged particle beam (as claimed in claim 6, such time required for the processing is optional).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LARRY LI whose telephone number is (571) 272-5043. The examiner can normally be reached 8:30am-4:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Robert Kim can be reached at (571) 272-2293. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LARRY LI/
Examiner, Art Unit 2881
/MICHAEL J LOGIE/ Primary Examiner, Art Unit 2881
Prosecution Insights