Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to the Applicant’s communication filed on 3 June 2024. In virtue of this communication, claims 1-8 are currently presented in the instant application.
Information Disclosure Statement(s)
The information disclosure statement(s) (IDS) submitted on 6/3/2024 is/are in compliance with the provisions of 37 CFR 1.97 and 1.98. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-8 rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claim(s) recite(s) mathematical calculations of a failure rate of a component. This judicial exception is not integrated into a practical application because a generic processor is considered to be simply implementing the abstract idea on a computer. The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the processor and memory are considered to be well-understood, routine, and conventional computer functions.
Claims 1-8 are also rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claim(s) recite(s) a mental process of evaluating a failure rate of a component. This judicial exception is not integrated into a practical application because a generic process is considered to be simply implementing the abstract idea on a computer. The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because it has been held that a claim that requires a computer may still recite a mental process.
Claims 2-7 do not impart any structural limitations that are sufficient to amount to significantly more. Claim 2 only requires that the evaluation is done to multiple components, claim 3 uses a mental step/normal calculation of a vague “upper limit”, which could be 100% to include all potential rates, and claim 4 specifies that the upper limit is the sum of the average value and the standard deviation which is just more manipulation of the data and known calculations (averaging the sum of a data set is well-known and routine and standard deviations are also known for defining a data set without the outliers).
With respect to claim 5, it is unclear how the first and second average values and the first and second standard deviations can be different as claimed (see the 112 below), and as above, does not impart significantly more than calculations or mental processes (standard deviations and average values and the manipulation of a data set).
With respect to claim 6, the calculations being repeated, or the mental process being repeated until a predetermined result is obtained is not considered to include elements that amount to significantly more.
With respect to claim 7, displaying the result of a calculation or mental process is not considered to include elements that amount to significantly more.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitations “calculates a first average value and a first standard deviation of the failure occurrence rate for each past model” and “calculates a second average value and a second standard deviation of the failure occurrence rate for each past model”. Both of these numbers should give the same result as the processor claims are not considered steps to be performed in order, and the way the second limitation is written. Language should be included in the second limitation that the second average value and second standard deviation is done on the previously filtered data from the previous step.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Fujiwara et al. (Patent No.: US 11,379,801 B2, herein known as D1).
With respect to claim 1, D1 discloses a component evaluation device (claim 2), comprising:
a processor and a memory coupled to the processor (one or more processors that are programmed to; claim 2, memory is inherent to the processor to perform the processes required), wherein the processor is configured to perform:
acquiring information regarding failure of a component input through an information input terminal after use of the component; calculating a failure occurrence rate of the component over time based on the information; and evaluating quality of a same type component of a type same as the component based on the failure occurrence rate (claim 2, processors detect based on sensors and predict the operational state of the steam traps based on predictive information, and deliver the results to maintenance personnel, in which the normal ranges are set by determining upper and lower limits of the “normal state”).
With respect to claim 2, D1 further discloses a device wherein the component is mounted on a plurality of models, wherein the processor: calculates the failure occurrence rate for each past model; and evaluates the quality of the same type component mounted on a new model based on the failure occurrence rate for each past model (claim 2, processors detect based on sensors and predict the operational state of the multiple steam traps based on predictive information, in which the normal ranges are set by determining upper and lower limits of the “normal state”).
With respect to claim 3, D1 further discloses a device wherein the processor: sets an upper limit value of a normal failure occurrence rate based on the failure occurrence rate for each past model; and evaluates the quality of the same type component mounted on the new model based on the upper limit value (claim 2, processors detect based on sensors and predict the operational state of the multiple steam traps based on predictive information, in which the normal ranges are set by determining upper and lower limits of the “normal state”; Column 11 lines 28-50 further describes using the average value and standard deviation to define the normal upper limit value and the normal upper limit value).
With respect to claim 4, D1 further discloses a device wherein the processor: calculates an average value and a standard deviation of the failure occurrence rate for each past model; and sets a sum of the average value and the standard deviation as the upper limit value (claim 2, processors detect based on sensors and predict the operational state of the multiple steam traps based on predictive information, in which the normal ranges are set by determining upper and lower limits of the “normal state”; Column 11 lines 28-50 further describes using the average value and standard deviation to define the normal upper limit value and the normal upper limit value).
With respect to claim 5, D1 further discloses a device wherein the processor: calculates a first average value and a first standard deviation of the failure occurrence rate for each past model; excludes the failure occurrence rate exceeding a sum of the first average value and the first standard deviation; calculates a second average value and a second standard deviation of the failure occurrence rate for each past model; and sets a sum of the second average value and the second standard deviation as the upper limit value (claim 2, processors detect based on sensors and predict the operational state of the multiple steam traps based on predictive information, in which the normal ranges are set by determining upper and lower limits of the “normal state”; Column 11 lines 28-50 further describes using the average value and standard deviation to define the normal upper limit value and the normal upper limit value; Column 11 lines 51-56 gives support of repeating the process and modifying the calculation reference if the accuracy is considered insufficient, with Column 11 line 57 – Column 12 line 63 detailing further steps).
See also the 112 rejection above.
With respect to claim 6, D1 further discloses a device wherein the processor repeats exclusion of the failure occurrence rate until a frequency distribution of the failure occurrence rate satisfies a predetermined condition (Column 11 lines 51-56 gives support of repeating the process and modifying the calculation reference if the accuracy is considered insufficient, with Column 11 line 57 – Column 12 line 63 detailing further steps).
With respect to claim 7, D1 further discloses a device wherein the processor notifies a quality evaluation result of the same type component (claim 2, notifies maintenance personnel).
With respect to claim 8, see claim 1 above (and also claim 1 of D1).
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Saxena et al. (Patent No.: US 11,533,247 B2)
Niu et al. (Publication No.: CN 114330006 A)
Hikuma et al. (Publication No.: JP 2020181468 A)
Thubert et al. (Publication No.: US 2020/0259746 A1)
Hu et al. (Publication No.: CN 111274687 A)
A machine translation of all foreign references are supplied with this Office Action.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIANA HANCOCK whose telephone number is (571)270-7547. The examiner can normally be reached on 10AM-6PM EST M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Stephanie Bloss can be reached on (571) 272-3555. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.H/Examiner, Art Unit 2852
5/30/2026
/STEPHANIE E BLOSS/Supervisory Primary Examiner, Art Unit 2852
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