DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 19 is objected to because of the following informalities:
The term “plurality of memory dies” in claim 19, lines 6-7 should be “the plurality of memory dies”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-13, 16, 19 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation "the logic circuit" in line 8. There is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation "the logic circuit" in line 3. There is insufficient antecedent basis for this limitation in the claim.
It is unclear whether “the logic circuit” in claims 10 and 11 is different from “logic circuitry” in claim 10, line 3.
The limitation “a second a second delay circuit” in claim, lines 1-2 is unclear
Claim 16 recites the limitation "the corresponding relative delay" in line 8. There is insufficient antecedent basis for this limitation in the claim.
Claim 19 recites the limitation "the corresponding delay value" in line 17. There is insufficient antecedent basis for this limitation in the claim.
Claim 19 recites the limitation "the clock signal" in line 15. There is insufficient antecedent basis for this limitation in the claim. It is unclear whether “the reference clock signal” and “the clock signal” are the same.
The recitation of “independently determine the corresponding delay value for each to the plurality of non-volatile memory dies” in claim 20, lines 3-4 is unclear. The term “each” does not clearly identify what element is in the claim.
Allowable Subject Matter
Claims 1-9, 14, 15, 17 and 18 are allowed.
Regarding claim 1, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “a transmitter circuit connected to the plurality of non-volatile memory dies, the transmitter circuit configured to: maintain, for each of the memory dies, a corresponding one of a plurality of delay values; select one of the memory dies for a data transfer; transmit a sequence of data values to the selected memory die; transmit a clock signal to the selected memory die for latching the data values of the sequence; and introduce a corresponding relative delay between the clock signal and the sequence of data values based on the corresponding delay value of the selected memory die.” in combination with the other limitations thereof as is recited in the claim. Claims 2-9 depend on claim 1.
Regarding claim 14, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of transmitting from the non-volatile memory controller to the non-volatile memory die a clock signal offset from the sequence of test data values by the delay value; latching the sequence of test data values in a receiver circuit on the non-volatile memory die using the transmitted clock signal offset by the delay value; and determining an amount of power consumed latching the sequence of test data values using the transmitted clock signal offset by the delay value; and for each of the non-volatile memory dies, selecting a corresponding one of the plurality of delay values based on the amount of power consumed latching the sequence of test data values using the transmitted clock signal offset by the plurality of delay values.” in combination with the other limitations thereof as is recited in the claim. Claims 15 and 17 depend on claim 14.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kakuru et al. (US 2025/0095753) discloses data path oscillator mismatch error correction reduction for non-volatile memory.
Li et al. (US 2025/0259969) discloses a high bandwidth non-volatile memory.
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/HUAN HOANG/Primary Examiner, Art Unit 2827