DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
3. Claim(s) 1-4, 11-12, is/are rejected under 35 U.S.C. 103 as being unpatentable over Jenne et al., US-6709928-B1.
Claims 1, 11. Jenne et al., disclose a semiconductor device (such as the one in figs. 1, 3A-3F, col. 3, ln 63+, and col. 5, ln 51+) comprising:
-a channel pattern (item 104, fig. 1);
-an electrode (item 112, fig. 1) over the channel pattern;
-and an information storage pattern (item 116) between the channel pattern and the electrode, wherein the information storage pattern comprises:
-a tunnel layer (item 114) adjacent to the channel pattern;
-a blocking layer (item 118) adjacent to the electrode;
-a charge trap layer (item 120) between the tunnel layer and the blocking layer;
-a first tunneling layer (layer on the bottom of item 120) disposed between the tunnel layer and the charge trap layer;
-and a second tunneling layer (layer on the upper of item 120) disposed between the charge trap layer and the blocking layer.
Jenne et al., disclose the invention, except the term “resonant” tunneling layer. However, Examiner notes by definition: Resonant tunneling is a quantum mechanical effect in which electrons tunnel through potential barriers in a semiconductor structure only when their energy matches a discrete, quantized energy level in a confined region (such as a quantum well).
As noted, (col 2, ln 7+) of Jenne et al., disclose in a conventional SONOS-type device 600, a programming operation may include establishing a potential between a substrate 602 and a control gate 604. Such a potential may cause electrons to tunnel from a substrate 602 through a tunnel dielectric 608 into a charge storing dielectric 610. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use resonant tunneling because it delivers fast, compact, and tunable device performance with NDR, making it ideal for high‑frequency, high‑speed, and specialized electronic applications.
Claims 2, 12. Jenne et al., disclose the semiconductor device according to claims 1, 11, wherein the first resonant tunneling layer includes a material having a lower energy barrier than the tunnel layer, and wherein the second resonant tunneling layer includes a material having a lower energy barrier than the charge trap layer (this limitation would read through (col 5, ln 63+) of Jenne et al., wherein is disclosed as shown in FIG. 3C, following the formation of a first part of a charge storing layer 304-0, a charge trapping layer 306 may be formed. A charge trapping layer 306, as noted above, may trap charge that could otherwise tunnel through a charge storing layer. A charge trapping layer 306 may be a layer that includes silicon-rich silicon nitride. Such a silicon-rich silicon nitride may have proportions of silicon that are greater than those of a first portion of a charge storing layer 304-0).
Claim 3. Jenne et al., disclose the semiconductor device according to claim 1, wherein the second resonant tunneling layer includes a material having a lower energy barrier than the blocking layer (this limitation would read through (col 5, ln 63+) of Jenne et al., wherein is disclosed as shown in FIG. 3C, following the formation of a first part of a charge storing layer 304-0, a charge trapping layer 306 may be formed. A charge trapping layer 306, as noted above, may trap charge that could otherwise tunnel through a charge storing layer. A charge trapping layer 306 may be a layer that includes silicon-rich silicon nitride. Such a silicon-rich silicon nitride may have proportions of silicon that are greater than those of a first portion of a charge storing layer 304-0).
Claim 4. Jenne et al., disclose the semiconductor device according to claim 1, wherein the first resonant tunneling layer includes a material having a lower energy barrier than the charge trap layer. (this limitation would read through (col 5, ln 63+) of Jenne et al., wherein is disclosed as shown in FIG. 3C, following the formation of a first part of a charge storing layer 304-0, a charge trapping layer 306 may be formed. A charge trapping layer 306, as noted above, may trap charge that could otherwise tunnel through a charge storing layer. A charge trapping layer 306 may be a layer that includes silicon-rich silicon nitride. Such a silicon-rich silicon nitride may have proportions of silicon that are greater than those of a first portion of a charge storing layer 304-0).
4. Claim(s) 5-10, 13-15, is/are rejected under 35 U.S.C. 103 as being unpatentable over Jenne et al., US-6709928-B1, in view of GE et al., US 2020/0235116 A1.
Claim 5. Jenne et al., disclose the semiconductor device according to claim 1, above.
Jenne et al., appear to not specify the first and the second resonant tunneling layers include tantalum pentoxide (Ta2O5), gallium oxide (Ga2O3), gadolinium oxide (Gd2O3), lanthanum oxide (La2O3), hafnium oxide (HfO2), gallium nitride (GaN), or a combination thereof.
In view of [0062] of GE et al., wherein is disclosed for example, dielectric metal oxides include aluminum oxide (Al.sub.2O.sub.3), hafnium oxide (HfO.sub.2), lanthanum oxide (LaO.sub.2), yttrium oxide (Y.sub.2O.sub.3), tantalum oxide (Ta.sub.2O.sub.5), silicates thereof, nitrogen-doped compounds thereof, alloys thereof, and stacks thereof. Thus, Jenne and GE have substantially the same environment of sequentially stacked a blocking layer adjacent to the electrode in charge-trapping memory structures. Therefore, one skilled in the art in at the time of invention would readily recognize incorporating an (Al.sub.2O.sub.3) material for the bonding material of Jenne et al., since the (Al.sub.2O.sub.3) would offers a high dielectric constant, excellent insulating properties, low trap density, high thermal/chemical stability, and compatibility with advanced fabrication processes. These characteristics make it ideal for high-performance, reliable, and long-lasting semiconductor devices, especially in memory, power electronics, and high-frequency applications, as taught by GE.
Claim 6. Jenne et al., disclose the semiconductor device according to claim 1, wherein the tunnel layer (item 302) includes silicon oxide (see col. 6, ln 27), the charge trap layer (items 304-0 and 304-1) includes silicon nitride.
Jenne et al., appear to not specify the blocking layer includes aluminum oxide.
In view of [0061] of GE et al., wherein is disclosed the blocking dielectric layer 52 can include a dielectric metal oxide. Further [0062] indicates examples of dielectric metal oxides include aluminum oxide (Al.sub.2O.sub.3). Thus, Jenne and GE have substantially the same environment of sequentially stacked a blocking layer adjacent to the electrode in charge-trapping memory structures. Therefore, one skilled in the art in at the time of invention would readily recognize incorporating an (Al.sub.2O.sub.3) material for the bonding material of Jenne et al., since the (Al.sub.2O.sub.3) would offers a high dielectric constant, excellent insulating properties, low trap density, high thermal/chemical stability, and compatibility with advanced fabrication processes. These characteristics make it ideal for high-performance, reliable, and long-lasting semiconductor devices, especially in memory, power electronics, and high-frequency applications, as taught by GE.
Claims 7-10, 14, 15. Jenne et al., disclose the semiconductor device according to claim 1, above.
Jenne et al., appear to not specify: wherein the first resonant tunneling layer has a thickness smaller than that of the tunnel layer (claim 7), wherein a thickness of the tunnel layer is 1 nm to 7 nm, and a thickness of the first resonant tunneling layer is 0.5 nm to 3 nm (claim 8); wherein the second resonant tunneling layer has a thickness smaller than that of the tunnel layer (claim 9); wherein a thickness of the tunnel layer is 1 nm to 7 nm, and a thickness of the second resonant tunneling layer is 0.5 nm to 3 nm (claim 10).
In view of [0063] of GE et al., wherein is disclosed the thickness of the dielectric semiconductor compound can be in a range from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed. Alternatively, the blocking dielectric layer 52 can be omitted, and a backside blocking dielectric layer can be formed after formation of backside recesses on surfaces of memory films to be subsequently formed. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have a thickness of the tunnel layer is 1 nm to 7 nm, and a thickness of the second resonant tunneling layer is 0.5 nm to 3 nm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Allen, 105 USPQ 233.
Claim 13. Jenne et al., disclose the semiconductor device according to claim 11, wherein the tunnel layer (item 302) includes silicon oxide (see col. 6, ln 27).
Jenne et al., appear to not specify the at least one resonant tunneling layer includes tantalum pentoxide (Ta2O5), gallium oxide (Ga2O3), gadolinium oxide (Gd2O3), lanthanum oxide (La2O3), hafnium oxide (HfO2), gallium nitride (GaN), or a combination thereof.
In view of [0062] of GE et al., wherein is disclosed for example, dielectric metal oxides include aluminum oxide (Al.sub.2O.sub.3), hafnium oxide (HfO.sub.2), lanthanum oxide (LaO.sub.2), yttrium oxide (Y.sub.2O.sub.3), tantalum oxide (Ta.sub.2O.sub.5), silicates thereof, nitrogen-doped compounds thereof, alloys thereof, and stacks thereof. Thus, Jenne and GE have substantially the same environment of sequentially stacked a blocking layer adjacent to the electrode in charge-trapping memory structures. Therefore, one skilled in the art in at the time of invention would readily recognize incorporating an (Al.sub.2O.sub.3) material for the bonding material of Jenne et al., since the (Al.sub.2O.sub.3) would offers a high dielectric constant, excellent insulating properties, low trap density, high thermal/chemical stability, and compatibility with advanced fabrication processes. These characteristics make it ideal for high-performance, reliable, and long-lasting semiconductor devices, especially in memory, power electronics, and high-frequency applications, as taught by GE.
Allowable Subject Matter
5. Claims 16-20 allowed.
Reasons for Allowance
6. The following is an examiner's statement of reasons for allowance:
7. Regarding Claims 16-20, the prior art failed to disclose or reasonably suggest a stack structure including a plurality of molding layers and a plurality of horizontal electrodes which are alternately stacked; a source line on the stack structure; and a channel structure passing through the stack structure, and extending into the source line, the channel structure comprising: a channel pattern contacting the source line; and an information storage pattern between the channel pattern and the stack structure, the information storage pattern comprising: a tunnel layer adjacent to the channel pattern; a blocking layer adjacent to the stack structure; a charge trap layer between the tunnel layer and the blocking layer; and at least one resonant tunneling layer disposed between the tunnel layer and the blocking layer, and including a material having a lower energy barrier than the tunnel layer and the blocking layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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